Patent classifications
H10N60/10
Systems and Methods for Superconducting Quantum Refrigeration
A heat transfer device and method are disclosed. The device includes a working region (i.e., working substance) made from a first superconducting material having a superconducting state and a normal state when magnetized. The first superconducting material has a first energy gap while in the superconducting state. A substrate (i.e., cold reservoir) is connected to the working region at a first tunnel junction. The substrate may be a metallic substrate. A heat sink (i.e., hot reservoir) is connected to the working region at a second tunnel junction. The heat sink is made from a second superconducting material having a second energy gap that is larger than the first energy gap. In a particular example, the heat transfer device includes a metallic substrate is made from Copper, a working region made from Tantalum, a heat sink made from Niobium, and the first and second tunnel junctions are made from Tantalum Oxide.
Superconducting clock conditioning system
One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a Josephson junction. The superconducting clock conditioning system is configured to receive an input AC clock signal and to output a conditioned AC clock signal having an approximately square-wave characteristic and having a peak amplitude that is less than a peak amplitude of the input AC clock signal.
Cooler device with superconductor shunts
A solid state cooler device is disclosed that includes a first superconductor shunt, a first normal metal pad disposed on the first superconductor shunt, and a first insulator layer and a second insulator layer disposed on the normal metal pad and separated from one another by a gap. The solid state cooler device also includes a first superconductor pad disposed on the first insulator layer and a second superconductor pad disposed on the second insulator layer, a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad. Hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad, wherein the first superconductor shunt facilitates even current distribution through the device.
Cryogenic detector with integrated backshort and method of manufacturing thereof
The present invention relates to an integrated reflective backshort fabricated with a phononic-isolated kinetic inductance detector or transition edge sensor. The integrated backshort includes: a silicon wafer; a reflective metal layer bonded to the silicon wafer; a silicon first layer disposed on the reflective metal layer; a structural second layer disposed on the first layer; a first superconductor layer disposed on the second layer as a kinetic inductance detector; and a second superconductor layer disposed on the second layer as leads, a microstrip, a capacitor or filter; wherein a phononic structure is etched in the second layer, leaving holes in the second layer; and wherein the etching penetrates through the holes into the second layer, and stopping on the reflective metal layer, leaving a space under the second layer where edges of the first layer etched under the second layer define a length of the integrated backshort.
Reducing qubit energy decay and correlated errors from cosmic rays in quantum processors
Large algorithms can be run on a quantum computer only if quantum error correction is used to lower logical qubit errors. The energy deposited by cosmic-ray muons produces a quasiparticle heat pulse that causes the qubits to decay in energy quickly, with errors correlated in space and time, so that error correction fails. Metal layers comprising normal metal and/or small-gap superconductors channel this energy away from the qubit into benign structures so that qubit performance is not degraded. These structures are designed according to the electron-phonon interactions and constraints from electromagnetic radiation to make large reductions in the induced errors so that error correction works properly.
Superconducting Diodes
A device may include a Josephson junction between at least three terminals. The device is configured to exhibit a superconducting diode effect. A method may include forming a Josephson layer including three terminals defining a Josephson junction. The method may further include forming, over the Josephson layer, a gate layer including at least three gates. Each gate of the at least three gates extends across a respective channel between a respective terminal pair of the three terminals. The Josephson layer and gate layer are configured to exhibit a superconducting diode effect.
Low-power biasing networks for superconducting integrated circuits
A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
SOLID STATE COOLER DEVICE
A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.
SUPERCONDUCTOR THERMAL FILTER
A superconductor thermal filter is disclosed that includes a normal metal layer having a first side, an insulating layer overlying the first side of the normal metal layer, and a multilayer superconductor structure having a first side overlying a side of the insulting layer opposite the side that overlies the normal metal layer. The multilayer superconductor structure is comprised of a plurality of superconductor layers with each superconductor layer having a smaller superconducting energy band gap than the preceding superconductor as the superconductor layers extend away from the normal metal layer. The thermal filter further includes a normal metal layer quasiparticle trap having a first side and a second side with the first side being disposed on a second side of the multilayer superconductor. A bias voltage is applied between the normal metal layer and the normal metal layer quasiparticle trap to remove hot electrons from the normal metal layer.
DURABLE HYBRID HETEROSTRUCTURES AND METHODS FOR MANUFACTURING THE SAME
A hybrid heterostructure includes a semiconductor layer comprising indium antimonide, a superconductor layer comprising aluminum, and a screening layer between the semiconductor layer and the superconductor layer, the screening layer comprising indium arsenide. By including a screening layer of indium arsenide between the semiconductor layer of indium antimonide and the superconductor layer of aluminum, a high-performance and durable hybrid heterostructure suitable for use in quantum computing devices is provided.