Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.

A thermalization arrangement at cryogenic temperatures is disclosed. The arrangement comprises a dielectric substrate layer on which substrate a device/s or component/s are positionable, and a heat sink component is attached on another side of the substrate. The arrangement further comprises a conductive layer between the substrate layer and the heat sink component. A joint between the substrate layer and the conductive layer has minimal phonon thermal boundary resistance. Energy of conductive layer phonons are arranged to be absorbed by electrons. Another joint between the conductive layer and the heat sink component is electrically conductive. The substrate layer and the conductive layer have similar acoustic properties

A thermalization arrangement at cryogenic temperatures is disclosed. The arrangement comprises a dielectric substrate layer on which substrate a device/s or component/s are positionable, and a heat sink component is attached on another side of the substrate. The arrangement further comprises a conductive layer between the substrate layer and the heat sink component. A joint between the substrate layer and the conductive layer has minimal phonon thermal boundary resistance. Energy of conductive layer phonons are arranged to be absorbed by electrons. Another joint between the conductive layer and the heat sink component is electrically conductive. The substrate layer and the conductive layer have similar acoustic properties

Aspects of the present disclosure are directed to quantum processing systems that include a plurality of donor atom qubits positioned in a semiconductor substrate. The system also comprises a plurality of control gates configured to control the donor atom qubits. The system further comprises an SLQD charge sensor fabricated on/in the semiconductor substrate. The SLQD charge sensor is configured to sense spin-states of two or more donor atom qubits, which are positioned within a sensing range of the SLQD charge sensor.

In a masking phase, a first segment of an amorphous mask is formed on an underlying layer of a substrate. The first segment comprises a first set of trenches exposing the underlying layer. In the masking phase, a second segment of the amorphous mask is formed on the underlying layer. The second segment comprises a second set of trenches exposing the underlying layer. The segments are non-overlapping. An open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends are separated by a portion of the amorphous mask. In a semiconductor growth phase, semiconductor material is grown, by selective area growth, in the first and second sets of trenches to form first and second sub-networks of nanowires on the underlying layer. The first and second sub-networks of nanowires are joined to form a single nanowire network.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

A circuit assembly for cooling a quantum electrical device, use of said circuit assembly, a system and a method for cooling a quantum electric device are provided. The circuit assembly comprises a quantum electric device to be cooled, at least one normal-metal-insulator-superconductor (NIS) tunnel junction electrically connected to the quantum electric device and at least one superconductive lead for supplying a drive voltage V.sub.QCR for said at least one NIS tunnel junction. The quantum electric device is cooled when the voltage V.sub.QCR is supplied to at least one NIS tunnel junction, said voltage V.sub.QCR being equal to or below the voltage N/e, where N=1 or N=2, N is the number of NIS tunnel junctions electrically coupled in series with the means for generating the voltage, is the energy gap in the superconductor density of states, and e is the elementary charge.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A milliohm resistor is fabricated as a Josephson junction device that contains ferromagnetic or antiferromagnetic material of sufficient thickness to render the device entirely resistive between terminals. The device can have a resistance on the order of milliohms and can be consume a much smaller chip footprint than resistors of the same resistance fabricated using conventional resistive materials. Because the device can be fabricated without modification to processes used to fabricate reciprocal quantum logic (RQL) circuitry, it can easily be incorporated in RQL circuits to mitigate flux trapping or to perform other functions where very small resistances are needed. In particular, the device can burn off circulating currents induced by trapped flux without affecting the transmission of SFQ pulses through RQL circuitry.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.