Patent classifications
H10N60/10
Low-power biasing networks for superconducting integrated circuits
A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
Reducing parasitic capacitance and coupling to inductive coupler modes
A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
Quantum computing devices with an increased channel mobility
Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.
Component for initializing a quantum dot
An electronic component (10) is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies (16, 18), for initializing the quantum mechanical state of a qubit.
SPIN QUBIT-TYPE SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT THEREOF
The invention provides a spin qubit-type semiconductor device capable of achieving both high-speed spin manipulation and high integration, and an integrated circuit for the spin qubit-type semiconductor device. The spin qubit-type semiconductor device includes a body comprised of at least one of a semiconductor layer itself formed with a quantum dot and a structural portion arranged around the semiconductor layer, a gate electrode arranged at a position on the semiconductor layer, which faces the quantum dot, at least one micro magnet wholly or partly embedded in the body so that a first position condition in which the micro magnet is at a position near the quantum dot, a second position condition in which the position of a lower end of the micro magnet is located below the gate electrode, and a third position condition in which when viewed from above the body, the micro magnet is arranged at a position having no rotational symmetry with the quantum dot as the center of rotation are satisfied, and a static magnetic field applying unit capable of applying a static magnetic field to the quantum dot and the micro magnet.
QUANTUM GATE DEVICE
A quantum gate device includes a first superconducting circuit which includes at least one of Josephson devices in an annular circuit including a superconducting wire and resonates at a first resonance frequency, a second superconducting circuit which includes at least one of Josephson devices in an annular circuit including a superconducting wire and resonates at a second resonance frequency, a connection unit which includes a capacitor and a superconducting wire provided at each electrode of the capacitor and connects the first and second circuits, a magnetic field application means applying a magnetic field to one or both of the first and second circuits, a quantum gate control electromagnetic wave irradiation unit irradiating one of the first and second circuits with a control electromagnetic wave, and an unnecessary transition suppression electromagnetic wave irradiation unit irradiating one of the first and second circuits with an unnecessary interaction suppression electromagnetic wave.
COOLER DEVICE WITH ALUMINUM OXIDE INSULATORS
A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.
SILICON SPIN QUANTUM BIT DEVICE AND MANUFACTURING METHOD THEREFOR
To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.
ARRAY OF QUANTUM DOTS WITH SPIN QUBITS
An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.
THERMALIZATION ARRANGEMENT AT CRYOGENIC TEMPERATURES
An inventive embodiment comprises a thermalization arrangement at cryogenic temperatures. The arrangement comprises a dielectric substrate (2) layer on which substrate a device/s or component/s (1) are positionable. A heat sink component (4) is attached on another side of the substrate. The arrangement further comprises a conductive layer (5) between the substrate layer (2) and the heat sink component (4). A joint between the substrate layer (2) and the conductive layer (5) has minimal thermal boundary resistance. Another joint between the conductive layer (5) and the cooling heat sink layer (4) is electrically conductive.