A system comprises a substrate having a planar surface; a first magnet configured to apply a first magnetic field parallel to the planar surface; a circuit arranged on the planar surface; and a superconducting quantum interference device, SQUID, operably linked to the circuit. The SQUID comprises a Josephson junction arranged in a superconductive loop. The superconductive loop includes a portion which extends perpendicular to the planar surface and is orientated such that the SQUID is tuneable by the first magnet. By allowing the SQUID to be tuned using a magnetic field which is parallel to the planar surface, a reduction in flux noise may be achieved. Also provided are a method of operating a SQUID, and a SQUID.

A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

A graphene/doped 2D layered material Van der Waals heterojunction superconducting composite structure, a superconducting device and a manufacturing method therefor, which relate to the technical field of superconducting materials. Said structure includes: a (2n+1)-layered structure formed by graphene layers and doped 2D layered materials which are alternately provided. An outer layer of the layered structure is the graphene layer, n is an integer between 1 to 50, a superconducting region is formed by a region in which the graphene perpendicularly overlaps the doped 2D layered material, and the graphene layers and the doped two-dimensional layered materials are self-assembled into one piece by means of a Van der Waals force.

A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.

A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

A circuit assembly for cooling a quantum electrical device, use of said circuit assembly, a system and a method for cooling a quantum electric device are provided. The circuit assembly comprises a quantum electric device to be cooled, at least one normal-metal-insulator-superconductor (NIS) tunnel junction electrically connected to the quantum electric device and at least one superconductive lead for supplying a drive voltage V.sub.QCR for said at least one NIS tunnel junction. The quantum electric device is cooled when the voltage V.sub.QCR is supplied to at least one NIS tunnel junction, said voltage V.sub.QCR being equal to or below the voltage NΔ/e, where N=1 or N=2, N is the number of NIS tunnel junctions electrically coupled in series with the means for generating the voltage, Δ is the energy gap in the superconductor density of states, and e is the elementary charge.

Techniques that can facilitate high-transparency semiconductor-metal interfaces are provided. In one example, a method can comprise forming a silicon on insulator (SOI) over a wafer. The method can further comprise depositing a metal on the SOI. The method can further comprise forming a structure by dry-etching the metal and dry-etching the SOI. The method can further comprise forming a template over the structure. The method can further comprise etching a portion of the SOI for removal under the metal. The method can further comprise growing a semiconductor where the portion of SOI was removed.

A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.