A superconducting quantum mechanical device includes first, second, third and fourth Josephson junctions connected in a bridge circuit having first, second and third resonance eigenmodes. The device also includes first and second capacitor pads. The first and second capacitor pads and the bridge circuit form a superconducting qubit having a resonance frequency corresponding to the first resonance eigenmode. The device further includes first and second resonator sections. The first and second resonator sections and the bridge circuit form a resonator having a resonance frequency corresponding to the second resonance eigenmode. The device also includes a source of magnetic flux arranged proximate the bridge circuit. The source of magnetic flux is configured to provide, during operation, a magnetic flux through the bridge circuit to cause coupling between the first, second and third resonance eigenmodes when the third resonance eigenmode is excited.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

A superconducting wire comprises a MgB.sub.2 filament, a base material, a high-thermal expansion metal, and a stabilizing material. The high-thermal expansion metal is a metal (for example, stainless steel) having a higher thermal expansion coefficient at room temperature than the MgB.sub.2 and the base material (for example, iron or niobium). The manufacturing method includes a step of packing a mixed powder in a first metal pipe, a step of performing wire-drawing on the first metal pipe formed of the metal to be the base material, a step of producing a composite wire by accommodating the first metal pipe in a second metal pipe formed of the high-thermal expansion metal and the stabilizing material, a step of performing wire-drawing on the composite wire, and a step of performing heat treatment.

A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).

High temperature superconductor (HTS)-based interconnect systems comprising a cable including HTS-based interconnects are described. Each of the HTS-based interconnects includes a first portion extending from a first end towards an intermediate portion and a second portion extending from the intermediate portion to a second end. Each of the HTS-based interconnects includes a substrate layer formed in the first portion, in the intermediate portion, and in the second portion, a high temperature superconductor layer formed in at least a sub-portion of the first portion, in the intermediate portion, and in the second portion, and a metallic layer formed in the first portion and in at least a sub-portion of the intermediate portion. The HTS-based interconnect system includes a thermal load management system configured to maintain the intermediate portion of each of the HTS-based interconnects at a predetermined temperature in a range between a temperature of 60 kelvin and 92 kelvin.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb.sub.2O.sub.5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb.sub.2O.sub.5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.

A wiring substrate capable of providing a through electrode having an insulating layer with a small dielectric loss is provided. A wiring substrate (50) includes a silicon substrate (40) formed of silicon whose electrical resistivity is 1000 Ω.Math.cm or larger and a through electrode (100) formed in the silicon substrate (40). The through electrode (100) is formed of a central conductor (110) that penetrates through the silicon substrate (40) and an external conductor (120, 130, 140) formed around the central conductor (110). The central conductor (110) and the external conductor (120, 130, 140) are electrically insulated from each other by the silicon substrate (40).

A connection structure of conductive layers according to an embodiment includes: a first conductive member including a first conductive layer and a first substrate, the first conductive member extending in a first direction, the first conductive member curved in the first direction such that the first conductive layer side is convex; a second conductive member including a second conductive layer and a second substrate, the second conductive member extending in the first direction, the second conductive member curved in the first direction such that the second conductive layer side is convex; a third conductive member including a third conductive layer and a third substrate, the third conductive member extending in the first direction; a first connection layer between a the first conductive layer and the third conductive layer, the first connection layer having varying thickness; and a second connection layer between the second conductive layer and the third conductive layer, the second connection layer having varying thickness.

A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions. In addition, the edge of the raised diffusion layer may be placed either in the gate region or the active layer region.