An airbridge implements connections on a superconducting chip. It comprises a strip of superconductive material between a first superconductive area and a second superconductive area. A first end of said strip comprises a first planar end portion attached to and parallel with said first superconductive area, and a second end of said strip comprises a respective second planar end portion. A middle portion is located between said first and second planar end portions, forming a bend away from a plane defined by the surfaces of the first and second superconductive areas. First and second separation lines separate the end portions from the middle portion. At least one of said first and second separation lines is directed otherwise than transversally across said strip.

The subject matter of the present disclosure may be embodied in devices, such as flexible wiring, that include: an elongated flexible substrate; multiple electrically conductive traces arranged in an array on a first side of the elongated flexible substrate; and an electromagnetic shielding layer on a second side of the elongated flexible substrate, the second side being opposite the first side, in which the elongated flexible substrate includes a fold region between a first electronically conductive trace and a second electrically conductive trace such that the electromagnetic shielding layer provides electromagnetic shielding between the first electronically conductive trace and the second electrically conductive trace.

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Techniques and methods to form smooth metal layers deposited onto selected surfaces of Josephson junction devices are provided. For example, one or more embodiments described herein can comprise depositing a layer of a first material comprising metal atom species on a selected surface of a device layer; depositing a layer of a second material on a surface of the layer of first material; and performing plasma etching on the layer of second material and the layer of first material to form an etched surface of the layer of first material that is smoother than the surface of the layer of first material, as deposited.

Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

A Josephson junction comprises superconducting electrodes (20) interconnected via an intermediate Josephson barrier (22), wherein the superconducting electrodes (20) and the intermediate Josephson barrier (22) are made out of the same chemical elements and are in a pristine condition.

Disclosed herein are assemblies for optical communication in quantum computing. For example, in some embodiments, a quantum computing assembly may include control circuitry having an optical interface to external electronic circuitry.

Systems and techniques that facilitate Stark shift cancellation are provided. In various embodiments, a system can comprise a control qubit that is coupled to a target qubit. In various cases, the control qubit can be driven by a first tone that entangles the control qubit with the target qubit. In various aspects, the control qubit can be further driven by a second tone simultaneously with the first tone. In various cases, the second tone can have an opposite detuning sign than the first tone. In various instances, the first tone can cause a Stark shift in an operational frequency of the control qubit, and the second tone can cancel the Stark shift.

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

A hard mask includes a silicon oxide layer provided on a bare silicon wafer; and a silicon nitride layer provided on the silicon oxide layer, wherein the silicon nitride is provided with a first pattern, the silicon oxide layer is provided with a second pattern corresponding to the first pattern, the first pattern and the second pattern have different shapes, and the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.