A structure has a substrate, and a spring structure disposed on the substrate, the spring structure having an anchor portion disposed on the substrate, an elastic material having an intrinsic stress profile that biases a region of the elastic material to curl away from the substrate, and a superconductor film in electrical contact with a portion of the elastic material. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.

A superconducting circuit includes a first component having a first connection point. The first connection point has a first width. The superconducting circuit includes a second component having a second connection point. The second connection point has a second width that is larger than the first width. The superconducting circuit includes a superconducting connector shaped to reduce current crowding. The superconducting connector electrically connects the first connection point and the second connection point. The superconducting connector includes a first taper positioned adjacent the first connection point and having a non-linear shape and a second taper positioned adjacent the second connection point.

A connection structure for a superconducting layer according to an embodiment includes a first superconducting layer; a second superconducting layer; and a connection layer disposed between the first superconducting layer and the second superconducting layer, the connection layer including crystal grains containing a rare earth element (RE), barium (Ba), copper (Cu), and oxygen (O), the crystal grains having a grain size distribution including a bimodal distribution. The bimodal distribution includes a first distribution including a first peak and a second distribution including a second peak. A first grain size corresponding to the first peak is larger than a second grain size corresponding to the second peak. Among the crystal grains, crystal grains having a grain size corresponding to the first distribution include a crystal grain having a plate shape or a flat shape.

A semiconductor device is fabricated by: forming a shadow wall on a substrate; subsequently growing a nanowire of semiconductor material on the substrate; and directionally depositing a layer of a further material on the nanowire from a direction selected such that the shadow wall casts a shadow on the nanowire, the shadow being a region in which the further material is not deposited. The nanowire is vertically orientated relative to the substrate. The shadow wall comprises a base portion and a bridge portion. The bridge portion overhangs the substrate and is supported by the base portion. Patterning of the further material may be achieved without the use of etching, thereby avoiding damage to the semiconductor. Also provided is a semiconductor-superconductor hybrid device; a quantum computing device comprising the semiconductor-superconductor hybrid device; and a shadow wall for controlling directional deposition of a material.

A semiconductor device is fabricated by: forming a shadow wall on a substrate; subsequently growing a nanowire of semiconductor material on the substrate; and directionally depositing a layer of a further material on the nanowire from a direction selected such that the shadow wall casts a shadow on the nanowire, the shadow being a region in which the further material is not deposited. The nanowire is vertically orientated relative to the substrate. The shadow wall comprises a base portion and a bridge portion. The bridge portion overhangs the substrate and is supported by the base portion. Patterning of the further material may be achieved without the use of etching, thereby avoiding damage to the semiconductor. Also provided is a semiconductor-superconductor hybrid device; a quantum computing device comprising the semiconductor-superconductor hybrid device; and a shadow wall for controlling directional deposition of a material.

Methods, systems, and apparatus for parallel optimization of continuously running quantum error correction by closed-loop feedback. In one aspect, a method includes continuously and effectively optimizing qubit performance in-situ whilst an error correction operation on the quantum system is running. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, where the errors attributable to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical qubits and operations are optimized. The method allows for the optimization of each section of a hardware pattern to be performed individually and in parallel, and can result is O(1) scaling.

A superconducting device includes two nodes and a Josephson junction coupled between the two nodes, wherein the Josephson junction is characterized by a superconducting phase difference, φ, wherein the superconducting device has a potential that varies as a function of the superconducting phase difference, φ, and has a single potential well. The potential has a non-zero cubic term and quartic term is zero. The Josephson junction may be a single small Josephson junction. The superconducting device may include a superconducting ring connected between the two nodes. The superconducting ring may include a first ring portion with a plurality of large Josephson junctions connected in series. The superconducting ring may also include a second ring portion that includes the single small Josephson junction in parallel with the plurality of large Josephson junctions between the two nodes.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Exemplary methods of fabricating high quality quantum computing components are described. The methods include removing native oxide from a deposition surface of a silicon substrate in a cleaning chamber of a processing system, and transferring the silicon substrate under vacuum to a deposition chamber of the processing system. The methods further include depositing an aluminum layer on the deposition surface of the silicon substrate in the deposition chamber, where an interface between the aluminum layer and the deposition surface of the silicon substrate is oxygen free.

One example includes a superconducting circuit. The circuit includes superconducting circuitry fabricated in a circuit layer. The circuit layer includes a first surface and a second surface opposite the first surface. The circuit also includes a flux moat comprising a dielectric material formed in the circuit layer. The flux moat can be configured to trap a magnetic flux as the superconducting circuit is cooled to below a superconducting critical temperature. The circuit further includes a magnetic film arranged proximal to the flux moat on at least one of the first and second surfaces of the circuit layer. The magnetic film can be configured to guide the magnetic flux to the flux moat as the superconducting circuit is cooled to below the superconducting critical temperature.