A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

A method may include forming a bottom electrode in an interlayer dielectric, depositing a liner on top of the bottom electrode, depositing a phase change material layer on top of the liner, wherein a top surface of the liner is in direct contact with a bottom surface of the phase change material layer, and depositing a barrier on top of the phase change material layer, wherein a top surface of the phase change material layer is in direct contact with a bottom surface of the barrier. The barrier may be made of doped phase change material. The forming of the bottom electrode may further include forming a via in the interlayer dielectric, depositing an outer layer along a bottom and a sidewall of the via, depositing a middle layer on top of the outer layer, and depositing an inner layer on top of the middle layer.

A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.

According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

The present invention provides methods to sputter deposit films comprising alkali metal compounds. At least one target comprising one or more alkali metal compounds and at least one metallic component is sputtered to form one or more corresponding sputtered films. The at least one target has an atomic ratio of the alkali metal compound to the at least one metallic component in the range from 15:85 to 85:15. The sputtered film(s) incorporating such alkali metal compounds are incorporated into a precursor structure also comprising one or more chalcogenide precursor films. The precursor structure is heated in the presence of at least one chalcogen to form a chalcogenide semiconductor. The resultant chalcogenide semiconductor comprises up to 2 atomic percent of alkali metal content, wherein at least a major portion of the alkali metal content of the resultant chalcogenide semiconductor is derived from the sputtered film(s) incorporating the alkali metal compound(s). The chalcogenide semiconductors are useful in microelectronic devices, including solar cells.

A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.