A method of forming a phase change switching device includes providing a substrate, forming first and second RF terminals on the substrate, forming a strip of phase change material on the substrate that is connected between the first and second RF terminals, forming a heating element adjacent to the strip of phase change material such that the heating element is configured to control a conductive state of the strip of phase change material. The first and second RF terminals and the heating element are formed by a lithography process that self-aligns the heating element with the first and second RF terminals

Provided herein are novel materials, such as novel phase-change memory materials providing superior characteristics, and methods of discovering/selecting such novel materials via machine learning, such as Bayesian active learning. An exemplary material provided by the inventive concept is the nanocomposite phase-change memory material Ge.sub.4Sb.sub.6Te.sub.7, selected using closed-loop autonomous materials exploration and optimization (CAMEO).

A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

Technologies for reducing series resistance are disclosed. An example method may comprise: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Technologies relating to increasing the surface area of selectors in crossbar array circuits are provided. An example apparatus includes: a substrate; a first line electrode formed on the substrate; an RRAM stack formed on the first line electrode, wherein the RRAM stack; an isolation layer formed beside the RRAM stack, wherein the isolation layer includes an upper surface and a sidewall, and a height from the upper surface to the first line electrode is 100 nanometers to 10 micrometers; a selector stack formed on the RRAM stack, the sidewall, and the upper surface; and a second line electrode formed on the selector stack.

A memory device includes a transistor and a memory cell. The memory cell includes a bottom electrode, a top electrode, and a dielectric structure. The top electrode is electrically connected to the transistor. The dielectric structure includes a thin portion and a thick portion. The thin portion is sandwiched between the bottom electrode and the top electrode. The thick portion is thicker than the thin portion and between the bottom electrode and the top electrode.

A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element that is deposited on the intermediate electrode. The resistive RAM module also comprises a sink electrode that is in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element and the memristor element is electrically between the intermediate electrode and the sink electrode.

A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.

A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.

Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.