An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

A memory device is provided that includes a method and structure for forming a resistive memory (RRAM) which has a gradual instead of abrupt change of resistance during programming, rendering it suitable for analog computing. In a first embodiment: One electrode of the inventive RRAM comprises a metal-nitride material (e.g., titanium nitride (TiN)) with gradually changing concentration of a metal composition (e.g., titanium). Different Ti concentrations in the electrode results in different concentration of oxygen vacancy in the corresponding section of the RRAM thereby exhibiting a gradual change of resistance dependent upon an applied voltage. The total conductance of the RRAM is the sum of conductance of each section of the RRAM. In a second embodiment: a RRAM with one electrode having multiple forks of electrodes with different composition concentration and thus different switching behaviors, rendering the inventive RRAM changing conductance gradually instead of abruptly.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first layer including a metal element on a substrate, and processing the first layer by dry etching. The method further includes removing a second layer formed on a lateral face of the first layer by wet etching, after processing the first layer, and forming a first film on the lateral face of the first layer by processing the lateral face of the first layer with a liquid, after removing the second layer. Furthermore, the substrate is not exposed to ambient air, after removing the second layer and before forming the first film.

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode.

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

A memory cell array of the present disclosure includes a plurality of memory cells 11 arranged in a first direction and a second direction different from the first direction. Each of the memory cells 11 includes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active region 80 provided in a semiconductor layer 60. At least a part of the active region 80 is in contact with an element isolation region 81 provided in the semiconductor layer 60. A surface of the element isolation region 81 is located at a position lower than a surface of the active region 80.