The disclosed technology generally relates to semiconductor devices and more particularly to memory or storage devices based on resistive switching, and to methods of making and using such devices. In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGe.sub.x, SiN.sub.x, AlO.sub.x, MgO.sub.x, AlN.sub.x, SiN.sub.x, HfO.sub.x, HfSiO.sub.x, ZrO.sub.x, ZrSiO.sub.x, GdAlO.sub.x, DyScO.sub.x, TaO.sub.x and combinations thereof. The second inner region comprises one or more silicon-containing layers, such that one of the one or more silicon-containing layers contacts the first inner region.

A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.

The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.

A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

The present invention relates to memristive devices including a resistance-switching element and a barrier element. In particular examples, the barrier element is a monolayer of a transition metal chalcogenide that sufficiently inhibits diffusion of oxygen atoms or ions out of the switching element. As the location of these atoms and ions determine the state of the device, inhibiting diffusion would provide enhanced state retention and device reliability. Other types of barrier elements, as well as methods for forming such elements, are described herein.

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M.sub.8XY.sub.6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M.sub.8XY.sub.6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

A semiconductor device may include: a memory cell disposed over a substrate and including a variable resistance layer and a selector layer; a protection layer disposed on side surfaces of the memory cell and an upper surface of the substrate on which the memory cell is not disposed; and a first encapsulation layer disposed on the memory cell and the protection layer, wherein the protection layer may include a treated surface that is modified by a material including helium.

A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×10.sup.20/cm.sup.3 to 1.0×10.sup.21/cm.sup.3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.