Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate; forming a layer of a correlated electron material on the conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; and patterning the layers whereby to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the patterning comprises the following steps: forming a hard mask on the layer of the conductive overlay; dry etching the layer of conductive overlay and the layer of correlated electron material whereby to form a partially formed stack; depositing a coating of a protective polymer over at least sidewalls of the partially formed stack; and dry etching the layer of conductive substrate.

Selector-based electronic devices, inverters, memory devices, and computing devices include a first selector and a second selector. The first selector and the second selector are electrically connected in series between a first voltage source terminal and a second voltage source terminal. The electronic device also includes a transistor electrically connected between an input terminal and a terminal between the first selector and the second selector.

A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

A surge protection device contains a first electrode, a second electrode electrically connected to electrical ground, and a field-induced switching component electrically contacting the first electrode and the second electrode. The field-induced switching component can include a correlated-electron material or a volatile conductive bridge.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.

This application concerns quantum computing, and in particular to structures and mechanisms for providing topologically protected quantum computation. In certain embodiments, a magnetic tunnel barrier is controlled that separates Majorona zero modes (MZMs) from an edge area (e.g., a gapless edge) of a quantum spin hall system. In particular implementations, the magnetic tunnel barrier is formed from a pair of magnetic insulators whose magnetization is held constant, and the magnetic tunnel barrier is tuned by controlling a gate controlling the electron density around the magnetic insulator in the QSH plane, thereby forming a quantum dot. And, in some implementations, a state of the quantum dot is read out (e.g., using a charge sensor as disclosed herein).

In a weak link of two s-wave superconductors (SCs) coupled via a time-reversal-invariant (TRI) topological superconducting (TSC) island, a Josephson current can flow due to Cooper pairs tunneling in and out of spatially separated Majorana Kramers pairs (MKPs), which are doublets of Majorana bound states (MBSs). The sign of the resulting Josephson current is fixed by the joint parity of the four Majorana bound states that make up the MKPs on the TSC island. This parity-controlled Josephson effect can be used as a read-out mechanism for the joint parity in Majorana-based quantum computing. For a TSC island with four terminals, the SC leads can address a Majorana superconducting qubit (MSQ) formed by the charge ground states of the TSC island's terminals. Cooper pair splitting enables single-qubit operations, qubit read-out, as well as two-qubit entangling gates. Hence, TSC islands between SC leads may provide an alternative approach to superconducting quantum computation.

Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.

Disclosed is a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (low impedance) state, wherein the forming of the CEM thin film comprises forming a d- or f-block metal or metal compound doped by a physical or chemical vapour deposition with a predetermined amount of a dopant comprising a back-donating ligand for the metal.