Disclosed is a transceiver that includes a three-dimensional array of Josephson junctions. When transmitting, the junctions drive an array of micro-antennas. When receiving, the micro-antennas drive the array of Josephson junctions. By extending the junction array into the third dimension, this transceiver packages a large number of Josephson junctions into a small volume, thus increasing the power of a transmitted beam. Multiple different micro-antenna arrays can be included, thus allowing the transceiver to work efficiently at multiple frequency ranges.

Electrical devices operating in a range of 273 C. to 100 C. are disclosed. The devices include an insulating substrate. A U0.sub.2+x crystal or oriented crystal U0.sub.2+x film is on a first portion of the substrate. The U0.sub.2+x crystal or film originates and hosts a non-equilibrium polaronic quantum phase-condensate. A first lead on a second portion of the substrate is in electrical contact with the U0.sub.2+x crystal or film. A second lead on a third portion of the surface is in electrical contact with the U0.sub.2+x crystal or film. The leads are isolated from each other. A U0.sub.2+x excitation source is in operable communication with the UO.sub.2+x crystal or film. The source is configured to polarize a region of the crystal or film thereby activating the non-equilibrium quantum phase-condensate. One source state causes the UO.sub.2+x crystal or film to be conducting. Another source state causes the U0.sub.2+x crystal or film to be non-conductive.

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

The film structure according to an embodiment of the present invention includes at least one active monolayer having an energy level quantized in at least one axial direction and at least one barrier alternately stacked with the at least one active monolayer. Current flows through the active monolayer, and the current flow may be limited by the quantized energy level.

A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes a coating step to coat a coating liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a UV irradiating step to form a UV-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the UV-irradiated coating films, after forming the plurality of UV-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the UV irradiating step.