This application concerns quantum computing, and in particular to structures and mechanisms for providing topologically protected quantum computation. In certain embodiments, a magnetic tunnel barrier is controlled that separates Majorona zero modes (MZMs) from an edge area (e.g., a gapless edge) of a quantum spin hall system. In particular implementations, the magnetic tunnel barrier is formed from a pair of magnetic insulators whose magnetization is held constant, and the magnetic tunnel barrier is tuned by controlling a gate controlling the electron density around the magnetic insulator in the QSH plane, thereby forming a quantum dot. And, in some implementations, a state of the quantum dot is read out (e.g., using a charge sensor as disclosed herein).

Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platform for performing universal TQC with Majorana wires in which explicit braiding need never occur. Thus, certain embodiments of the disclosed technology involve three synergistically connected aspects of anyonic TQC (in the context of the currently active area of using MZMs for topological quantum computation): a practical phase gate for universal topological quantum computation using MZMs, a precise protocol (using CHSH inequality) for testing that the desired gate operation has been achieved, and bypassing the necessity of MZM braiding (and so avoiding, e.g., problems of nonadiabaticity in the braids).

Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

An optical sensor is disclosed. The optical sensor may include a substrate, a topological insulator layer formed on the substrate, an oxide layer formed on the topological insulator layer, a graphene layer stacked on the oxide layer, and a dielectric layer covering the graphene layer.

A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

A method for forming a semiconductor structure comprising quantum dots with self-aligned gate structures is disclosed. The method comprises structuring a doped silicon-on-isolator to build a source area, a linear structure extending from the source area having at least two distinct broadened areas, a first and a second gate structure simultaneously by a single lithography process; covering the structures with a blanket oxide layer, forming an opening in the blanket oxide layer at a lateral end of the linear structure, etching back the linear structure and the at least two distinct broadened areas below the blanket oxide until the source area is reached, and filling the hollow template with a semiconductor material different to the silicon such that the at least two broadened areas build quantum dot areas.

A quantum computing system and methods for performing fault-tolerant quantum computing. A fusion controller sequentially performs a series of fusion measurements on different fusion sites of a plurality of fusion sites to obtain a respective series of classical measurement results. The series of fusion measurements is performed on quantum modes of a logical qubit. For respective fusion measurements of the series of fusion measurements, a basis for performing the respective fusion measurement is selected based on classical measurement results of previous fusion measurements. The series of classical measurement results are in the memory medium.

One example includes a flux qubit readout circuit. The circuit includes a gradiometric SQUID that is configured to inductively couple with a gradiometric flux qubit to modify flux associated with the gradiometric superconducting quantum interference device (SQUID) based on a flux state of the flux qubit. The circuit also includes a current source configured to provide a readout current through the gradiometric SQUID during a state readout operation to determine the flux state of the gradiometric flux qubit at a readout node.

An ion trap device is provided as well as a method of manufacturing the ion trap device including a substrate, central DC electrode, RF electrode, side electrode and an insulating layer. Disposed over the substrate, the central DC electrode includes DC connector pad and DC rail connected thereto. The RF electrode includes RF rail adjacent to the DC rail and RF pad connected to RF rail. The side electrode has RF electrode disposed between thereof and the central DC electrode. The insulating layer supports one of the central DC electrode, RF electrode and side electrode, on a top surface of the substrate. The insulating layer includes first insulating layer and second insulating layer disposed over the first insulating layer, and the second insulating layer includes an overhang protruding with respect to the first insulating layer in a width direction of the ion trap device.

Surface supported quantum wells with a confined surface state capture and stably confine neutral atoms and molecules in a nanometer precise environment. Depending on the physico-chemical conditions in the capturing process, the degree of occupancy, the temperature of the solid substrate, and/or the history of external stimuli like electromagnetic field pulses, these atoms, molecules or clusters assume unique configurations. The atoms or molecules are able to remain coupled to the quantum-well specific electronic state in the confinement and as such exhibit local and delocalized quantum entanglement. The capturing potential arises from the superposition of Pauli repulsion between the captured object and the quantum well-specific confined electronic state. This occurs within on-surface atomic or supramolecular assemblies or surface supported coordination or covalent networks.