Methods for utilizing irradiation to selectively transform insulating self-developing resists, such as metal fluorides, into electrically conductive metals are described. The disclosed methods enable the fabrication of electrical components and structures with critical dimensions below 5 nanometers. Selective irradiation induces the conversion of insulating metal fluoride compounds into metals in predefined regions. Examples of applications include miniature wiring, quantum point contacts, miniature electroplating and via-holes fabrication by using fluoride as etching mask.

A device for quantum information processing is disclosed herein. According to examples, the device comprises a first plurality of confinement regions for confining spinful charge carriers for use as data qudits. The device further comprises a second plurality of confinement regions for confining spinful charge carriers for use as ancillary qudits, each confinement region of the second plurality of confinement regions couplable to measurement apparatus for measuring an ancillary qudit. The device further comprises a third plurality of confinement regions for confining spinful charge carriers, each confinement region of the third plurality of confinement regions situated between a first confinement region of the first plurality of confinement regions and a second confinement region of the second plurality of confinement regions and for use in mediating interactions between a data qudit of the first confinement region and an ancillary qudit of the second confinement region. The device further comprises one or more charge reservoirs. Each confinement region of the third plurality of confinement regions is couplable to a charge reservoir of the one or more charge reservoirs. Methods for operating a device for quantum information processing, and computer-readable media, are also described herein.

Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platform for performing universal TQC with Majorana wires in which explicit braiding need never occur. Thus, certain embodiments of the disclosed technology involve three synergistically connected aspects of anyonic TQC (in the context of the currently active area of using MZMs for topological quantum computation): a practical phase gate for universal topological quantum computation using MZMs, a precise protocol (using CHSH inequality) for testing that the desired gate operation has been achieved, and bypassing the necessity of MZM braiding (and so avoiding, e.g., problems of nonadiabaticity in the braids).

Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough.

One example includes a flux qubit readout circuit. The circuit includes a gradiometric SQUID that is configured to inductively couple with a gradiometric flux qubit to modify flux associated with the gradiometric superconducting quantum interference device (SQUID) based on a flux state of the flux qubit. The circuit also includes a current source configured to provide a readout current through the gradiometric SQUID during a state readout operation to determine the flux state of the gradiometric flux qubit at a readout node.

A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one electrode 5A and the other electrode 5B disposed so as to have a nanosize gap in between; a nanoparticle 7 placed between the nanogap electrodes 5; and a plurality of gate electrodes 9. At least one of the plurality of gate electrodes 9 is used as a floating gate electrode to control the state of electric charge of the nanoparticle 7, which achieves a multivalued memory and rewritable logical operation.

Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platforms for performing universal TQC with Majorana wires in which explicit braiding need never occur. Thus, certain embodiments of the disclosed technology involve three synergistically connected aspects of anyonic TQC the context of the currently active area of using MZMs for topological quantum computation): a practical phase gate for universal topological quantum computation using MZMs, a precise protocol (using CHSH inequality) for testing that the desired gate operation has been achieved, and bypassing the necessity of MZM braiding (and so avoiding, e.g., problems of nonadiabaticity in the braids).

A phononic transistor can be realized by arranging a row of cantilevered structures with attached magnets, elastically extending upward upon application of a magnetic repulsive force to the magnets. In the extended configuration, the phonons are transmitted from source to drain, while in the flattened configuration the phonons are blocked from transmission. A gate element controls the ON and OFF states of the phononic transistor.

A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.