An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.

An ultra-low-profile low frequency antenna including a magnetic core having coil winding channels in three intersecting axial directions orthogonal to each other, defining X-axis (X), Y-axis (Y) and Z-axis (Z), receiving respective X-coil (DX), Y-coil (DY), and Z-coil (DZ). A Z-coil winding channel surrounds the magnetic core around the Z-axis (Z), providing partial grooves confined between two parallel surfaces. The thickness of the magnetic core in the Z-axis (Z) is less than 1.2 mm. Each partial groove has a width in the Z-axis (Z) equal or less than 0.4 mm and its depth in a radial direction perpendicular to the Z-axis (Z) is at least two times of its width. The Z-coil (DZ) is wound within said groove and extends radially from ⅓ to ⅔ of the groove's depth. The outer edge of the Z-coil is at the entrance of the groove.

A multilayer inductor is provided. The multilayer inductor includes a multilayer winding portion comprising a plurality of coil layers that are vertically stacked, and having an inner surface that defines a hollow of the plurality of coil layers and having an outer surface that defines an outer side and a magnetic compensator made of a soft magnetic material and comprising a magnetic wall located at at least one of the inner surface or the outer surface of the multilayer winding portion.

A semiconductor device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the conductive lines.

A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a base, wherein the base is provided with a first surface and a second surface that are opposite to each other; a magnetic core, wherein the magnetic core is located in the base, and an orthographic projection of the magnetic core on the first surface is a closed ring pattern; a dielectric layer, wherein the dielectric layer is located on the second surface; and a solenoid-shaped metal layer, wherein the metal layer is located in the base and the dielectric layer and is wound around the magnetic core; the metal layer is an integrated structure; the metal layer and the magnetic core are spaced apart from each other; part of the metal layer is exposed on the first surface.

Provided is a package structure including a first die; a plurality of through vias, aside the first die; a first encapsulant laterally encapsulating the first die and the plurality of through vias; a first redistribution layer (RDL) structure on first sides of the first die, plurality of through vias, and the first encapsulant; a second RDL structure on second sides of the first die, the plurality of through vias, and the first encapsulant; and a plurality of conductive connectors, electrically connected to the second RDL structure. Portions of the first RDL structure, the plurality of through vias, and the second RDL structure are electrically connected to each other and form a solenoid inductor laterally aside the first die.

A semiconductor device includes a semiconductor substrate, an interconnect structure, and a permalloy device. The interconnect structure is disposed over the semiconductor substrate. The interconnect structure includes a conductive coil. The conductive coil includes horizontally-extending metal lines, and vertically-extending vias electrically connecting the metal lines. The permalloy device is disposed in the interconnector structure and wound around by the conductive coil and insulated by the conductive coil, wherein the permalloy device and the conductive coil in combination define an inductor, and the permalloy device serves as a magnetic core of the inductor.

An electronic component with a plurality of coil conductor layers laminated such that a coil conductor having a coil pattern on a surface of an insulation layer is formed on each of the plurality of coil conductor layers. The electronic component includes a laminated body in which a bottom face side extended electrode layer, a primary coil conductor layer including a primary coil conductor, a secondary coil conductor layer including a secondary coil conductor, a tertiary coil conductor layer including a tertiary coil conductor, a parallel primary coil conductor layer including a parallel primary coil conductor, and a top face side extended electrode layer are laminated in this order. The electronic component further includes first through sixth external electrodes on a surface of the laminated body, which are connected to the primary, secondary, tertiary and parallel primary coil conductors.