A glass-ceramic-ferrite composition containing a glass, a ferrite, and a ceramic filler, in which the glass contains, by weight, about 0.5% to about 5.0% R.sub.2O (R represents at least one selected from the group consisting of Li, Na, and K), about 5.0% or less Al.sub.2O.sub.3, about 10.0% to about 25.0% B.sub.2O.sub.3, and about 70.0% to 85.0% SiO.sub.2 with respect to the total weight of the glass, the percentage by weight of the ferrite is about 10% to 80% with respect to the total weight of the composition, the ceramic filler contains at least forsterite selected from forsterite and quartz, the percentage by weight of the forsterite is about 1% to about 10% with respect to the total weight of the composition, and the percentage by weight of the quartz is about 40% or less with respect to the total weight of the composition.

An embedded inductance structure includes an insulating layer, an inductance located in the insulating layer, a multi-layer conducting circuit located in the insulating layer and on the upper surface and lower surface of the insulating layer, and a multi-layer conductive copper column layer located in the insulating layer. The inductance and the multi-layer conducting circuit are conductively connected via the multi-layer conductive copper column layer, and the inductance includes a magnet and an inductance coil in direct contact with the magnet, and the inductance coil is composed of a multi-layer conductive coil and a conductive copper column located between adjacent conductive coils. The multi-layer conductive coils are respectively in a ring shape with a notch and are disconnected at the notch, and the positions of the conductive copper columns located on the upper side and lower of each conductive coil are different in the longitudinal direction.

A module includes a wiring board, an insulating layer that is laminated on the bottom surface of the wiring board, a ring-shaped coil core that is embedded in the insulating layer, a coil electrode that is wound around the coil core, electronic components that are disposed in an inner region surrounded by the coil core in the insulating layer, and an electronic component that is mounted on or in the top surface of the wiring board. With this configuration, the areas of main surfaces of the wiring board and main surfaces of the insulating layer are not large, whereas if the electronic components were mounted on or in the top surface of the wiring board, the areas of the main surfaces of the wiring board and the main surfaces of the insulating layer would be large, and a reduction in the size of the module can be facilitated.

A manufacturing method of a package includes at least the following steps. A carrier is provided. An inductor is formed over the carrier. The inductor includes a first portion, a second portion, and a third portion. The first portion is parallel to the third portion, and the second portion connects the first portion and the third portion. A die is placed over the carrier. The die is surrounded by the inductor. An encapsulant is formed between the first portion and the third portion of the inductor. The encapsulant laterally encapsulates the die and the second portion of the inductor.

An inductor package is described comprising a mold interconnection substrate having an embedded spiral coil inductor, a fan-out redistribution layer connected to the spiral coil inductor by a copper post wiring structure, a ferrite toroid coil in between the copper posts, and a semiconductor die mounted on the mold interconnection substrate and connected to the fan-out redistribution layer.

A coil component includes a support member, an internal coil supported by the support member and including a plurality of coil patterns, and external electrodes connected to the internal coil and including a first layer in contact with the internal coil and a second layer disposed on the first layer. The second layer is a composite layer including a conductive material and a resin. The support member includes first and second surfaces facing the external electrodes, respectively, and one or more of at least a portion of the first surface and at least a portion of the second surface are configured as cut surfaces.

A coil component capable of matching characteristic impedance (Zo) includes an insulating layer in which coil conductors are embedded; a first magnetic member disposed to be in contact with one surface of the insulating layer; and a second magnetic member having permeability lower than that of the first magnetic member and disposed to be in contact with the other surface of the insulating layer. An interval L1 between the second magnetic member and the coil conductors depends on an intended impedance value.

A coil component includes an insulating layer; an annular ring-shaped coil core embedded in the insulating layer; a coil electrode wound around the coil core; an input electrode designed for external connection, disposed on a lower surface of the insulating layer, and connected to a first end of the coil electrode; and an output electrode designed for external connection, disposed on the lower surface of the insulating layer, and connected to a second end of the coil electrode. One of the input electrode and the output electrode is disposed inside the coil core in a plan view. With this configuration, unlike a conventional coil component in which both input and output electrodes are disposed outside a coil core, it is possible not only to easily reduce the area of the coil component in a plan view, but also to improve heat dissipation characteristics of the coil component.

A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric layer over the lower coil segment and the first dielectric layer, anisotropically etching a top portion of the second dielectric layer to form an opening over the lower coil segment, depositing magnetic material in the opening to form a magnetic core, forming a third dielectric layer over the magnetic core and the second dielectric layer, forming vias extending through the second dielectric layer and the third dielectric layer, and after forming the vias, forming an upper coil segment over the third dielectric layer and the magnetic core, wherein the vias connect the upper coil segment with the lower coil segment.