There are provided a chip electronic component and a board having the same. The chip electronic component includes: a substrate; a first internal coil part disposed on one surface of the substrate; a second internal coil part disposed on the other surface of the substrate opposing one surface thereof; a via penetrating through the substrate to connect the first and second internal coil parts to each other; and first and second via pads disposed on one surface and the other surface of the substrate, respectively, to cover the via, wherein the first and second via pads are extended in a direction toward portions of the first and second internal coil parts adjacent thereto.

An inductor includes a coil that is provided in a component body. A first end of the coil is connected to a first outer electrode, and a second end of the coil is connected to a second outer electrode. The coil includes a plurality of coil conductor layers that are provided in a width direction. Each coil conductor layer is substantially spirally formed with the number of turns being greater than or equal to about one turn. The height of the component body is greater than the width of the component body.

An inductor device includes a first trace, a second trace, and a double ring inductor. The first trace is disposed at a first area. The second trace is disposed at a second area. The double ring inductor is located at an outside of the first trace and the second trace. The double ring inductor is respectively coupled to the first trace and the second trace in an interlaced manner.

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.

An inductor device includes a first trace, a second trace, an input/output terminal, a center-tapped terminal, and an interlaced connection portion. The first trace is located on a first layer. The second is located on the first layer. The input/output terminal is disposed at a first side of the inductor device. The center-tapped terminal is disposed at a second side of the inductor device. The interlaced connection portion is disposed at a third side or a fourth side of the inductor device, and coupled to the first trace or the second trace. No interlaced connection structure is disposed along a connection line between the input/output terminal and the center-tapped terminal.

The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

An inductor component comprising a base body comprising a filler; a coil in the base body and helically wound along an axis; and external electrodes in the base body and each electrically connected to the coil, with outer faces of the external electrodes exposed from the base body. The base body comprises external electrode contact parts that each contact one of the external electrodes on an inner side of the base body and are each disposed along one of the external electrodes; and a central part that comprises a center point of the base body and is located away from the coil, the external electrodes, and the external electrode contact parts. A content rate of the filler in the external electrode contact parts is from a 0.9-fold level to a 1.1-fold level of a content rate of the filler in the central part.

The coil substrate may include a substrate; a first conductor layer including a plurality of first and second segments periodically disposed on a top and a bottom of the substrate; a second conductor layer including a plurality of first and second segments periodically overlapping the first conductor layer on the top and the bottom of the substrate; a first connection line that connects the first and second segments of the first conductor layer; and a second connection line that connects the first and second segments of the second conductor layer. The first connection line includes a first region exposed on at least one of first and second surfaces that are opposite to each other of the substrate and second and third regions disposed through the substrate from both sides of the first region.