An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.

An electronic component includes an element body including two end surfaces opposite to each other and a bottom surface connected between the two end surfaces. A coil is provided in the element body and an external electrode is provided in the element body. In a first cross-section intersecting with the two end surfaces and the bottom surface of the element body, the external electrode has a first portion extending along a first surface that is one of the end surface and the bottom surface of the element body. The coil is disposed such that an outer circumferential edge of the coil faces the first surface of the element body. A shortest distance between the outer circumferential edge of the coil and the first surface of the element body is smaller than a minimum width of the first portion in a direction orthogonal to the first surface.

A coil electronic component includes a support substrate having a through-hole. First and second coil patterns are disposed on a first surface and a second surface of the support substrate opposing each other, respectively, and each surround the through-hole and are coiled. An encapsulant encapsulates at least portions of the support substrate and the first and second coil patterns, and external electrodes are disposed externally of the encapsulant and are each connected to a respective lead-out pattern connected to a respective one of the first and second coil patterns. A groove penetrates the first surface of the support substrate in a region of the first surface in which the first coil pattern is not disposed, and the second coil pattern is disposed in a region of the second surface of the support substrate that overlaps along a thickness direction with the groove penetrating the first surface.

An electronic component includes a glass ceramic layer and a conductor layer. The glass ceramic layer includes feldspar crystal phases, non-crystalline glass phases, and Al.sub.2O.sub.3 phases. The area ratio of the feldspar crystal phases in the vicinity of the conductor layer is larger than the area ratio of the feldspar crystal phases away from the conductor layer.

An inductor includes a semiconductor substrate provided with a plurality of wiring levels including a first wiring level and a second wiring level, a straight conductive line, at the first wiring level of the semiconductor substrate, having a first end, a conductive coil of a spiral pattern, at the second wiring level over the first wiring level, having a second end, and a conductive via vertically connecting the first end of the straight conductive line to the second end of the conductive coil. When viewed in a plan view, a plurality of dummy patterns are arranged in a first area defined by an innermost turn of the spiral pattern.

An inductor includes a coil that is provided in a component body. A first end of the coil is connected to a first outer electrode, and a second end of the coil is connected to a second outer electrode. The coil includes a plurality of coil conductor layers that are provided in a width direction. Each coil conductor layer is substantially spirally formed with the number of turns being greater than or equal to about one turn. The height of the component body is greater than the width of the component body.

There are provided a chip electronic component and a board having the same. The chip electronic component includes: a substrate; a first internal coil part disposed on one surface of the substrate; a second internal coil part disposed on the other surface of the substrate opposing one surface thereof; a via penetrating through the substrate to connect the first and second internal coil parts to each other; and first and second via pads disposed on one surface and the other surface of the substrate, respectively, to cover the via, wherein the first and second via pads are extended in a direction toward portions of the first and second internal coil parts adjacent thereto.

An inductor device includes a first and a second inductor. First inductor includes plural first wires and a first connection member. Second inductor includes plural second wires and a second connection member. Part of first wires are winded/located at a first area, and part of first wires are winded/located at a second area. First and second areas are located on two opposite sides of inductor device. First connection member connects first wire located at first area and located at second area. Part of second wires are winded/located at first area, and part of second wires are winded/located at second area. One terminal of second connection member connects a terminal of second wire at an inner side of inductor device, and another terminal of second connection member is disposed outside inductor device. First and second inductors are symmetrical with respect to a center line of inductor device.

There are provided a chip electronic component and a board having the same. The chip electronic component includes: a substrate; a first internal coil part disposed on one surface of the substrate; a second internal coil part disposed on the other surface of the substrate opposing one surface thereof; a via penetrating through the substrate to connect the first and second internal coil parts to each other; and first and second via pads disposed on one surface and the other surface of the substrate, respectively, to cover the via, wherein the first and second via pads are extended in a direction toward portions of the first and second internal coil parts adjacent thereto.

A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.