An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

A semiconductor package may include a substrate, including an inductor array including inductor structures, and a semiconductor chip and a voltage regulator each on the substrate. Each of the inductor structures may include an input terminal, an output terminal, a coil between the input terminal and the output terminal, and conductive wirings. The inductor structures may be apart from one another in a second horizontal direction. Each of the coils may include a lower horizontal winding wound horizontally, an upper horizontal winding wound horizontally, and a conductive via. In a plan view, the coils may be arranged in zigzags, and the coils and the conductive wirings may be alternately arranged in the second horizontal direction.

A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.

A method of fabricating an inductor includes (a) forming a ferromagnetic core on a semiconductor substrate, the ferromagnetic core lying in a core plane and (b) fabricating an inductor coil that winds around the ferromagnetic core, the inductor coil configured to generate an inductor magnetic field that passes through the ferromagnetic core in a first direction parallel to the core plane. While forming the ferromagnetic core, the method further includes (1) generating a bias magnetic field that passes through the ferromagnetic core in a second direction that is orthogonal to the first direction, and (2) inducing a magnetic anisotropy in the ferromagnetic core with the bias magnetic field.

An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

An electronic component includes a first insulating layer, a high-voltage electrode formed on the first insulating layer, a low-voltage electrode formed on the first insulating layer so as to be spaced from the high-voltage electrode, and an uneven structure formed in a region between the high-voltage electrode and the low-voltage electrode along a surface of the first insulating layer.

A semiconductor die includes a processing circuit, a first bond pad, and a second bond pad. The first bond pad is electrically connected to a first node of the processing circuit and a first bond wire. The second bond pad is electrically connected to a second node of the processing circuit and a second bond wire. The first bond wire and the second bond wire are magnetically coupled to form a first bond wire T-coil circuit with equivalent negative inductance.

A semiconductor device includes a semiconductor substrate, an insulating layer, a transformer formed in the insulating layer, and a wiring. The transformer includes a primary winding conductor, and a secondary winding conductor. The primary winding conductor is provided in a quadrangle spiral shape having a first center axis extending in a direction parallel to the surface of the semiconductor substrate inside the insulating layer, and configured by one conductor film selected from a group consisting of a vacuum deposition film, a chemical vapor deposition film and a sputtered film. The secondary winding conductor is provided in a quadrangle spiral shape having a second center axis inside the insulating layer while being spaced from the primary winding conductor in plan view of the semiconductor substrate, magnetically coupled with the primary winding conductor and configured by a conductor film.

A multi-phase buck switching converter having grouped pairs of phases, each phase using two magnetically coupled air-core inductors. For each group, a first driver circuit controlling switching of a first power transistor switching circuit coupled to a first air-core inductor output for driving an output load at the first phase. A second driver circuit controlling switching of a second power transistor switching circuit coupled to a second air-core inductor output for driving said output load at the second phase. The first and second phases are spaced 180° apart. The coupled air-core inductors per group of such orientation, separation distance and mutual inductance polarity relative to each other such that magnetic coupling between the two or more inductors at each phase results in a net increase in effective inductance per unit volume. Each air-core inductor is a metal slab of defined length, height and thickness formed using back-end-of-line semiconductor manufacturing process.

Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.