A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

A magnetic random access memory (MRAM) array includes a plurality of MRAM cells, each of the MRAM cells including a magnetic tunnel junction (MTJ) stack disposed on a bottom metal via connecting the MTJ stack to a bottom conductive contact in a substrate, a plurality of top conductive contacts, each of the top conductive contacts disposed on a respective one of the MTJ stacks, and a plurality of unitary structures configured as a heat sink/magnetic shield disposed on a vertical portions of each of the MRAM cells, including vertical portions of the bottom metal vias, and under a portion of each of the MTJ stacks.

A magnetic random access memory (MRAM) array includes a plurality of MRAM cells, each of the MRAM cells including a magnetic tunnel junction (MTJ) stack disposed on a bottom metal via connecting the MTJ stack to a bottom conductive contact in a substrate, a plurality of top conductive contacts, each of the top conductive contacts disposed on a respective one of the MTJ stacks, and a plurality of unitary structures configured as a heat sink/magnetic shield disposed on a vertical portions of each of the MRAM cells, including vertical portions of the bottom metal vias, and under a portion of each of the MTJ stacks.

Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.

Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.

An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.

Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening.