A capacitor bank that includes at least two capacitors wherein the capacitor bank is configured to change the quantity of phases of the input voltage within the capacitor bank. The capacitor bank of the preferred embodiment of the present invention includes a first capacitor and a second capacitor. The first capacitor and second capacitor are three phase capacitors each having three terminals configured to couple to an input voltage. The capacitor bank is wired so as to have a first source of an input voltage coupled to two terminals of the first capacitor and one terminal of the second capacitor. A second source of the input voltage is electrically coupled to one terminal of the first capacitor and two terminals of the second capacitor. The capacitor bank is operable to change the double phase input voltage into three phases within the capacitor bank.

The present disclosure provides a chip part. The chip part is capable of ensuring a greater capacitance of a capacitor, maintaining stability of walls and enhancing stability of components. The chip part includes: a substrate, having a first main surface and a second main surface opposite to the first main surface; a capacitive film, disposed on the first main surface; a first external electrode, disposed on the capacitive film; a second external electrode, disposed on the second main surface; and a conductive layer, disposed between the capacitive film and the substrate. A vertical capacitor having a laminated structure of an upper electrode (first external electrode)-capacitive film-lower electrode (substrate) is formed in a lengthwise direction along the thickness direction of the substrate.

The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.

The present disclosure provides a chip part. The chip part includes a substrate, a capacitor portion and a substrate body portion. The capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on a first main surface of the substrate. The substrate body portion is formed around the capacitor portion using a portion of the substrate. The plurality of wall portions are formed of a plurality of pillar units. The capacitor portion, in the plan view, includes a first capacitor portion and a second capacitor portion. The first capacitor portion includes the plurality of wall portions having the lengthwise direction as a first lengthwise direction. The second capacitor portion includes the plurality of wall portions having the lengthwise direction as a second lengthwise direction orthogonal to the first lengthwise direction.

A capacitor module that includes: a plurality of capacitors each including: a first electrode and a second electrode that face each other, and a side surface joining the first electrode and the second electrode, the side surface having a pair of flat portions that face each other, and a pair of curved portions joining the pair of flat portions to each other, the plurality of capacitors being arrayed in a row such that the flat portions of adjacent capacitors face each other; at least one metal sheet arranged in any of spaces between the flat portions of the adjacent capacitors, the at least one metal sheet being in contact with the first electrode of at least one of the adjacent capacitors; a first bus-bar electrically connected to the at least one metal sheet; and a second bus-bar electrically connected to each of the second electrodes of the plurality of capacitors.

A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal.

Disclosed is a broadband capacitor including floating electrodes arranged above and below a laminate in which electrode units are laminated to allow easy change of the characteristic (that is, a capacitance value) of a capacitor. The disclosed broadband capacitor comprises: a dielectric; a first external electrode; a second external electrode; a laminate, which is disposed in the dielectric and in which a plurality of electrode units are laminated; an upper floating electrode disposed in the dielectric, disposed above the laminate, and overlapping the first external electrode and the second external electrode; and a lower floating electrode disposed in the dielectric, disposed below the laminate, and overlapping the first external electrode and the second external electrode.

An apparatus includes a case having an elliptical cross-section capable of receiving a plurality of capacitive elements. One or more of the capacitive elements provide at least one capacitor having a first capacitor terminal and a second capacitor terminal. The apparatus also includes a cover assembly that includes a deformable cover mountable to the case, and, a common cover terminal having a contact extending from the cover. The cover assembly also includes at least three capacitor cover terminals, each of the at least three capacitor cover terminals having at least one contact extending from the deformable cover. The deformable cover is configured to displace at least one of the at least three capacitor cover terminals upon an operative failure of at least one of the plurality of the capacitive elements. The cover assembly also includes at least four insulation structures. One of the four insulation structures is associated with one of the at least three capacitor cover terminals. The apparatus also includes a first conductor capable of electrically connecting the first capacitor terminal of a capacitor provided by one of the plurality of capacitive elements to one of the at least three capacitor cover terminals and a second conductor capable of electrically connecting the second capacitor terminal of the capacitor provided by one of the plurality of capacitive elements to the common cover terminal.

A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

A multilayer capacitor includes a laminate having a first side surface and a second side surface, a first side covering portion covering the first side surface, and a second side covering portion covering the second side surface. The laminate includes first conductor layers, second conductor layers, dielectric layers and insulating layers laminated in the z direction. Each first conductor layer is connected to the first side covering portion and spaced apart from the second side covering portion. Each second conductor layer is connected to the second side covering portion and spaced apart from the first side covering portion. The insulating layers have a lower dielectric strength than the dielectric layers. Each dielectric layer is sandwiched between a first conductor layer and a second conductor layer. The insulating layers include one sandwiched between two first conductor layers and one sandwiched between two second conductor layers.