A multi-terminal multilayer capacitor includes first vias and second vias extending in first and second internal electrodes in a stacking direction, a first slit extending between the first via and a first insulating portion that insulates the second via and the first internal electrode from each other, and a second slit extending between the second via and a second insulating portion that insulates the first via and the second internal electrode from each other. The first via electrically connects regions of the first internal electrode split by the first slit, and the second via electrically connects regions of the second internal electrode divided by the second slit.

The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.

A multilayer wiring substrate and a module having the multilayer wiring substrate, wherein the multilayer wiring substrate has a capacitor with a capacitance value smaller than that of the conventional one. The substrate includes a core substrate and capacitors installed therein. At least one of the capacitors is a first capacitor which includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is located closer to the core substrate than the dielectric layer and the upper electrode are. The upper electrode is located farther away from the core substrate than the dielectric layer and the lower electrode are. The lower electrode is entirely disposed on the core substrate. The upper electrode has a first portion and a second portion. The first portion overlaps the dielectric layer and the lower electrode to serve as the first capacitor. The second portion extends from the first portion.

A capacitor includes at least one multi-wing structure; a laminated structure, where the laminated structure clads the at least one multi-wing structure and includes at least one dielectric layer and a plurality of conductive layers, and the at least one dielectric layer and the plurality of conductive layers form a structure that a conductive layer and a dielectric layer are adjacent to each other; at least one first external electrode, where the first external electrode is electrically connected to some conductive layer(s) in the plurality of conductive layers; at least one second external electrode, wherein the second external electrode is electrically connected to the other conductive layer(s) in the plurality of conductive layers, and a conductive layer in the laminated structure adjacent to each conductive layer in the some conductive layer(s) includes at least one conductive layer in the other conductive layer(s).

A multi-layer capacitor including a capacitor element having at least two segments. Each segment includes multiple layer planes, including ceramic dielectric layers and electrode layers arranged therebetween, which are arranged in a layer sequence one above the other. The electrode layers include different electrodes, including at least first and second electrodes. The different electrodes overlap in active regions but not in passive regions. Multiple segments are arranged one above the other in a stack direction. The outermost dielectric layers of two segments form a connection region in which the segments are fixedly connected to each other parallel to the layer planes. The connection region contains a relief region. The relief region occupies at least the entire passive region of the capacitor.

A filter unit according to the present invention includes a substrate, capacitors mounted on the substrate, and two inductors. The inductors each include a wire and a core. The core includes two core bodies. The core bodies each have a ring shape and include a wiring hole. The capacitors are disposed between the two core bodies. An opposed section extends from the respective two core bodies to a position opposed to the capacitors C. The opposed section is opposed to all of the plurality of capacitors.

An apparatus suitable for use in an air-conditioning system and configured to provide a plurality of selectable capacitance values includes a plurality of capacitive devices and a pressure interrupter cover assembly. Each of the capacitive devices has a first capacitor terminal and a second capacitor terminal. The pressure interrupter cover assembly includes a deformable cover, a set of capacitor cover terminals, a common cover terminal, and a set of insulation structures. The apparatus also includes a conductor configured to electrically connect the second capacitor terminal of at least one of the capacitive devices to the common cover terminal.

A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

An electronic component of a multi-layered structure includes a laminate formed by stacking a plurality of ceramic bodies and an external electrode made of a conductive resin for connecting each ceramic body.