A power fuse for protecting an electrical load subject to transient load current cycling events in a direct current electrical power system is provided. The power fuse includes at least one fuse element assembly that includes an elongated planar substrate, a plurality of fusible weak spots, and a conductor. The weak spots are formed on the substrate and are longitudinally spaced from one another on the substrate. The conductor is separately provided from the substrate and the weak spots. The conductor includes a solid elongated strip of metal having no stamped weak spot openings therein and therefore avoiding thermal-mechanical fatigue strain in the conductor when subjected to the transient load current cycling events. The solid elongated strip of metal includes coplanar connector sections that are mounted to respective ones of the weak spots and obliquely extending sections bent out of plane of the connector sections to extend above the substrate.

The present disclosure discloses a miniature super surface mount fuse, comprising: a fuse element provided with a low overload fusing point and at least two high breaking capacity fusing points connected in series with the low overload fusing point and respectively arranged on two sides of the low overload fusing point, at least two cavity plates provided with cavities, the low overload fusing point and the high breaking capacity fusing points being located at corresponding positions of the cavities; the present disclosure further provides a manufacturing method for a surface mount fuse; the miniature super surface mount fuse of the present disclosure can provide the protection for the civil consumer electronic circuit under various overload conditions without the occurrence of safety hazards such as smoking or cracking of the housing or explosion.

A high breaking capacity chip fuse including a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement in the aforementioned order, a fusible element disposed between the first and second intermediate insulative layers and extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers are formed of porous ceramic.

A power fuse for protecting an electrical load subject to transient load current cycling events in a direct current electrical power system is provided. The power fuse includes at least one fuse element assembly that includes an elongated planar substrate, a plurality of fusible weak spots, and a conductor. The weak spots are formed on the substrate and are longitudinally spaced from one another on the substrate. The conductor is separately provided from the substrate and the weak spots. The conductor includes a solid elongated strip of metal having no stamped weak spot openings therein and therefore avoiding thermal-mechanical fatigue strain in the conductor when subjected to the transient load current cycling events. The solid elongated strip of metal includes coplanar connector sections that are mounted to respective ones of the weak spots and obliquely extending sections bent out of plane of the connector sections to extend above the substrate.

A novel temperature-triggered fuse device is configured to be activated at a designer-specified ambient temperature by utilizing wetting force among a pair of wetting material bays and a solder bridge or a solder ball. The solder bridge or the solder ball is typically positioned on top of the pair of wetting material bays separated by an electrically-insulated gap. Preferably, the wetting material bays are at least partly made of gold, nickel, or other elements suitable for generating an increased wetting force to the solder bridge or the solder ball upon increases in ambient temperature. The novel temperature-triggered fuse device can be integrated into various types of integrated circuits (IC's), or can function as a discrete fuse connected to one or more electronic components for robust protection from power surges and/or thermal runaway-related device malfunctions, meltdowns, or explosions. Various methods of producing the temperature-triggered fuse device are also disclosed herein.

A surface-mountable thin-film fuse component is disclosed that may include a substrate having a top surface, a first end, and a second end that is spaced apart from the first end in a longitudinal direction. The thin-film component may include a fuse layer formed over the top surface of the substrate. The fuse layer may include a thin-film fuse track. An external terminal may be disposed along the first end of the substrate and electrically connected with the thin-film fuse track. The external terminal may include a compliant layer comprising a conductive polymeric composition.

A mandrel structure includes a first mandrel, a second mandrel and a third mandrel in a parallel arrangement. The second mandrel is located between the first and third mandrels and has a cut larger than a minimum ground rule feature. A sidewall layer is formed over the mandrel structure. The sidewall layer has two long parallel gaps for two contact lines and a third gap for a fuse element. The third gap is orthogonal to and connects the two long parallel gaps. The sidewall pattern is used to form a trench structure comprising two parallel contact line trenches having a width at least as great as a ground rule of the patterning process for the contact lines and an orthogonal fuse element trench having a width less than the ground rule for the fuse element. A conductive material forms the contact lines and a fuse element.

A fuse element, in particular suited for use in electric and/or electronic circuits constructed by multilayer technology, including a printed circuit board substrate material, which is usable particularly in the multilayer technology and is coated with a metal or metal alloy from which the fuse is generated by means of photolithographic and/or printing image-producing techniques and ensuing etching or engraving processes, is proposed. The fuse is distinguished in that the printed circuit board substrate material, on which the fuse can be provided, includes at least a high-temperature-stable, electrically insulating material, with a coefficient of thermal expansion that varies essentially analogously to the coefficient of thermal expansion of the metal or metal alloy from which the fuse is made.

A novel temperature-triggered fuse device is configured to be activated at a designer-specified ambient temperature by utilizing wetting force among a pair of wetting material bays and a solder bridge or a solder ball. The solder bridge or the solder ball is typically positioned on top of the pair of wetting material bays separated by an electrically-insulated gap. Preferably, the wetting material bays are at least partly made of gold, nickel, or other elements suitable for generating an increased wetting force to the solder bridge or the solder ball upon increases in ambient temperature. The novel temperature-triggered fuse device can be integrated into various types of integrated circuits (IC's), or can function as a discrete fuse connected to one or more electronic components for robust protection from power surges and/or thermal runaway-related device malfunctions, meltdowns, or explosions. Various methods of producing the temperature-triggered fuse device are also disclosed herein.

A circuit board with integrated fusing includes an insulating substrate having a circuit trace formed on a surface thereof, the circuit trace including a first circuit trace portion and a second circuit trace portion. A fusible link electrically connects the first circuit trace portion to the second circuit trace portion, the fusible link including a planar surface extending from the first circuit trace portion to the second circuit trace portion. A dielectric reflow encapsulates the fusible link on the planar surface from the first circuit trace portion to the second circuit trace portion.