H01L21/02002

SUPPORT SUBSTRATE FOR BONDED WAFER

A handle wafer used for a bonded wafer that is produced by bonding an active wafer and the handle wafer through an insulation film is provided. The handle wafer includes a handle wafer body and a polycrystalline silicon layer deposited on a side close to a bonding surface of the handle wafer body. The polycrystalline silicon layer has a polycrystalline silicon grain size of 0.419 μm or less.

GaN/DIAMOND WAFERS
20230231019 · 2023-07-20 ·

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

N-type silicon single crystal production method, n-type silicon single crystal ingot, silicon wafer, and epitaxial silicon wafer

In a producing method of an n-type monocrystalline silicon by pulling up a monocrystalline silicon from a silicon melt containing a main dopant in a form of red phosphorus to grow the monocrystalline silicon, the monocrystalline silicon exhibiting an electrical resistivity ranging from 0.5 mΩcm to 1.0 mΩcm is pulled up using a quartz crucible whose inner diameter ranges from 1.7-fold to 2.3-fold relative to a straight-body diameter of the monocrystalline silicon.

SiC epitaxial wafer and method for manufacturing same
11705329 · 2023-07-18 · ·

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

Substrate for electronic device and method for producing the same

A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 μm, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 Ωcm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.

Semiconductor-on-insulator (SOI) substrate and method for forming

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Fabrication of high-aspect ratio nanostructures by localized nanospalling effect

In this work is presented a method for fabrication of high-aspect ratio structures through spalling effect. The spalling is achieved through lithography, etching and sputtering processes, thus providing the flexibility to position the spalled structures according to the application requirements. This method has been successfully demonstrated for metal-oxides and metals. The width of the fabricated structures is dependent on the thickness of the film deposited by sputtering, where structures as small as 20 nm in width have been obtained.

LASER MACHINING APPARATUS, LASER MACHINING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMBER
20230219172 · 2023-07-13 · ·

A laser processing device includes: a light source configured to output laser light; a space light modulator for modulating the laser light output from the light source in accordance with a modulation pattern and outputting the modulated laser light; a converging lens for converging the laser light output from the space light modulator to an object, and forming a converging spot on the object; a movement unit for relatively moving the converging spot with respect to the object; and a control unit for relatively moving, while setting a position of the converging spot in a Z direction intersecting with an incident surface of the laser light on the object at a first Z position, the converging spot along a line extended in an X direction along the incident surface by controlling at least the space light modulator and the movement unit.

Method for producing a layer of solid material

A method for producing a layer of solid material includes: providing a solid body having opposing first and second surfaces, the second surface being part of the layer of solid material; generating defects by means of multiphoton excitation caused by at least one laser beam penetrating into the solid body via the second surface and acting in an inner structure of the solid body to generate a detachment plane, the detachment plane including regions with different concentrations of defects; providing a polymer layer on the solid body; and generating mechanical stress in the solid body such that a crack propagates in the solid body along the detachment plane and the layer of solid material separates from the solid body along the crack.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.