A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline SiC, the donor substrate comprising a donor layer produced by epitaxial growth on an initial substrate, the donor layer exhibiting a density of crystal defects that is lower than that of the initial substrate; b) a step of ion implantation of light species into the donor layer, in order to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free face of the donor layer; c) a succession of n steps of formation of carrier layers, with n greater than or equal to 2, the n carrier layers being arranged on the donor layer successively on one another and forming the carrier substrate, each step of formation comprising a chemical vapor deposition, at a temperature of between 400° C. and 1100° C., in order to form a carrier layer made of polycrystalline SiC, the n chemical vapor depositions being carried out at n different temperatures; d) a step of separation along the buried brittle plane, in order to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the remainder of the donor substrate; and e) a step of mechanical and/or chemical treatment(s) of the composite structure.

A semiconductor device has a first substrate made of a first semiconductor material, such as silicon. A sacrificial layer is formed over a first surface of the first substrate. A seed layer is formed over the sacrificial layer. A compliant layer is formed over a second surface of the first substrate opposite the first surface of the first substrate. A first semiconductor layer made of a second semiconductor material, such as silicon carbide, dissimilar from the first semiconductor material is formed over the sacrificial layer. The first substrate and sacrificial layer are removed leaving the first semiconductor layer substantially defect-free. The first semiconductor layer containing the second semiconductor material is formed at a temperature greater than a melting point of the first semiconductor material. A second semiconductor layer is formed over the first semiconductor layer with an electrical component formed in the second semiconductor layer.

A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

A method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film, wherein the method includes forming a SiC film on one principal surface side of a Si substrate and forming a recessed part in which a bottom surface is Si in a central part of another principal surface of the Si substrate.

A SiC ingot includes: a main body including a first cross-sectional plane of the main body and a second cross-sectional plane of the main body facing the first cross-sectional plane; and a protrusion disposed on the second cross-sectional plane and including a convex surface from the second cross-sectional plane of the main body, wherein a first end point disposed at one end of the second cross sectional plane, a second end point disposed at another end of the second cross sectional plane, and a peak point disposed on the convex surface are disposed on a third cross-sectional plane of the main body perpendicular to the first cross-sectional plane, and wherein a radius of curvature of an arc corresponding to a line of intersection between the third cross-sectional plane and the convex surface satisfies Equation 1 below:
3D≤r≤37D  [Equation 1]
where r is the radius of curvature of the arc corresponding to the line of intersection between the third cross-sectional plane and the convex surface, and D is a length of a line of intersection between the first cross-sectional plane and the third cross-sectional plane.

A device chip manufacturing method includes attaching a wafer to the first surface of a semiconductor ingot, separating the semiconductor ingot into a subject part and a remaining part after attachment, the subject part being attached to the wafer to form a laminated wafer having a front side as an exposed surface of the subject part and a back side as an exposed surface of the wafer, setting a plurality of crossing division lines on the front side of the laminated wafer to thereby define a plurality of separate regions after separation, and next forming a plurality of devices in the respective separate regions, and then dividing the laminated wafer along the division lines after forming the devices, thereby forming the plural device chips including the respective devices.

The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a handle substrate having a plurality of bulk macro defects (BMDs). An insulating layer is disposed onto a top surface of the handle substrate. A device layer, including a semiconductor material, is disposed onto the insulating layer. The handle substrate has a first denuded region and a second denuded region that vertically surround a central region of the handle substrate. The central region has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

A composite structure, intended for a planar co-integration of electronic components of different functions, the composite structure including from its base towards its surface: a support substrate made of a first material, the support substrate including cavities each opening into an upper face of the support substrate, the cavities being filled with at least one composite material consisting of a matrix of a crosslinked preceramic polymer, the matrix being charged with inorganic particles; and a thin film made of a second material, the thin film being bonded to the upper face of the support substrate and to the composite material.

A method for manufacturing a film, notably monocrystalline, on a flexible sheet, comprises the following steps: providing a donor substrate, forming an embrittlement zone in the donor substrate so as to delimit the film, forming the flexible sheet by deposition over the surface of the film, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the flexible sheet.

A method is used to prepare the remainder of a donor substrate, from which a layer has been removed by delamination in a plane weakened by ion implantation. The remainder comprises, on a main face, an annular step corresponding to a non-removed part of the donor substrate. The method comprises the deposition of a smoothing oxide on the main face of the remainder in order to fill the inner space defined by the annular step and to cover at least part of the annular step, as well as heat treatment for densification of the smoothing oxide. A substrate is produced by the method, and the substrate may be used in subsequent processes.