A film-forming apparatus and film-forming method comprising, a chamber, a first gas supply unit supplying a reaction gas for a film-forming process to the chamber, a substrate-supporting portion supporting a substrate placed in the chamber, a heating unit heating the substrate from below the substrate-supporting portion, a rotary drum supporting the substrate-supporting portion on a top thereof, and including the heating unit disposed therein, a rotary shaft disposed in a lower part of the chamber, and rotating the rotary drum, a reflector reflecting heat from the heating unit, surrounding the rotary drum, and being disposed so as to have an upper end higher in height than an upper end of the substrate-supporting portion, and a second gas supply unit supplying a hydrogen gas or an inert gas between the rotary drum and the reflector.

Embodiments of the invention relate generally to directed self-assembly (DSA) and, more particularly, to the DSA of electronic components using diamagnetic levitation.

A method for forming a semiconductor device structure is provided. The method includes forming a stack over a substrate. The stack has multiple sacrificial layers and multiple oxide semiconductor layers laid out alternately. The method also includes partially removing the sacrificial layers to expose inner portions of the oxide semiconductor layers. The inner portions of the oxide semiconductor layers form multiple oxide semiconductor nanostructures. The method further includes changing an atomic concentration of oxygen of the oxide semiconductor nanostructures. In addition, the method includes forming a gate stack wrapped around one or more of the oxide semiconductor nanostructures after the changing of the atomic concentration of oxygen of the oxide semiconductor nanostructures.

Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed.

A liquid treatment method includes: supplying a first organic solvent to a substrate with the substrate being held horizontally by a substrate holder; and thereafter supplying a second organic solvent to a substrate held by the substrate holder, the second solvent having a higher cleanliness than the first solvent.

An amount of particles generated when a source material is used is suppressed. A substrate is loaded into a process chamber, and the source material is sequentially flowed into an evaporator, and a mist filter constituted by assembling a plurality of at least two types of plates including holes disposed at different positions to be evaporated and supplied into the process chamber to process the substrate, and then, the substrate is unloaded from the process chamber.

Embodiments of the present disclosure describe light emitting displays having a light emitter layer that includes an array of light emitters and a wafer having a driving circuit coupled with the light emitter layer, computing devices incorporating the light emitting displays, methods for formation of the light emitting displays, and associated configurations. A light emitting display may include a light emitter layer that includes an array of light emitters and a wafer coupled with the light emitter layer, where the wafer includes a driving circuit formed thereon to drive the light emitters. Other embodiments may be described and/or claimed.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.