A method is disclosed that includes operations as follows: after forming an ion-implanted layer disposed between an epitaxial layer and a first semiconductor substrate, bounding the epitaxial layer to a bonding oxide layer without forming any layer between the epitaxial layer and the bonding oxide layer; and removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping a remaining portion of the ion-implanted layer on the epitaxial layer.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.

A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a first color conversion layer over each of a first plurality of light emitting diodes, a second color conversion layer over each of a second plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array. The micro-LEDs of the array are configured to generate illumination of the same wavelength range, the first color conversion layer converts the illumination to light of a first color, and the second color conversion layer converts the illumination to light of a different second color.

A preprocessing method comprises a sintering step of heating a solid material container filled with a solid material using a temperature which is lower than either the melting point or sublimation of the solid material, whichever is lower, and crystallizing at least part of the solid material, and an impurity removal step of heating the solid material container filled with the solid material using a temperature which is lower than either the melting point or sublimation of the solid material, whichever is lower, and removing at least part of the impurities included in the solid material.

A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a color conversion layer over each of a plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array.

An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to train a machine-learning model based on the input data reflecting the feature. The manufacturing system is further configured to modify the machine-learning model in view of the virtual knob for the feature.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.