A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.

A Schottky barrier diode according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.

An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.

A method for forming an electrical contact is provided. The method includes grinding a silicon carbide surface using a grinding disk which includes a grinding face containing nickel or a nickel compound, such that particles of the nickel or nickel compound from the grinding disk are embedded in the ground silicon carbide surface, and hardening the ground silicon carbide surface with the aid of a laser, such that at least some of the embedded nickel particles form a nickel silicide with silicon from the silicon carbide.

A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.

A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

First p.sup.+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p.sup.+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p.sup.+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p.sup.+-type regions and the trenches. Drain-side edges of the second p.sup.+-type regions are positioned closer to a source side than are drain-side edges of the first p.sup.+-type regions. In each mesa region, an n.sup.+-type region is provided separate from the first p.sup.+-type regions and the trenches. The n.sup.+-type regions are adjacent to and face the second p.sup.+-type regions in the depth direction.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.