SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME

Abstract

A Schottky barrier diode according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

Claims

1. A Schottky barrier diode comprising: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer, the p+ type region and the p type region separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on a plane, and is arranged in a matrix shape, and the n− type layer, which is disposed between the p+ type region and the p type region, has a hexagonal shape on the plane and encloses the p type region.

2. The Schottky barrier diode of claim 1, wherein a horizontal line, which passes through a center point of the p type region, does not meet a horizontal line of the p type region that is adjacent thereto in a column direction on the plane.

3. The Schottky barrier diode of claim 2, wherein the p+ type region and the p type region respectively contact the n− type layer, and an area where the p+ type region and the n− type layer contact is wider than an area where the p type region and the n− type layer contact.

4. The Schottky barrier diode of claim 3, wherein an ion doping concentration of the p+ type region is higher than an ion doping concentration of the p type region.

5. The Schottky barrier diode of claim 4, wherein the anode includes a Schottky electrode, and the cathode includes an ohmic electrode.

6. The Schottky barrier diode of claim 5, further comprising an n type layer disposed between the anode and the n− type layer, and the ion doping concentration of the n type layer is higher than the ion doping concentration of the n− type layer.

7. The Schottky barrier diode of claim 6, further comprising a first trench and a second trench disposed on the n type layer, the first trench and the second trench separated from each other.

8. The Schottky barrier diode of claim 7, wherein the p+ type region is disposed under a bottom surface of the first trench, and the p type region is disposed under the bottom surface of the second trench.

9. The Schottky barrier diode of claim 8, wherein the anode includes a first anode disposed inside the first trench and the second trench, and a second anode disposed on the first anode and the n type layer.

10. A method for manufacturing a Schottky barrier diode, comprising: sequentially forming an n− type layer and an n type layer at a first surface of an n+ type silicon carbide substrate; forming a first trench and a second trench separated from each other at the n type layer; injecting a p+ type ion to a bottom surface of the first trench to form a p+ type region; injecting a p type ion to the bottom surface of the second trench to form a p type region; forming an anode on the n type layer, inside the first trench, and inside the second trench; and forming a cathode at a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on a plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane, and encloses the p type region.

11. The method of claim 10, wherein a horizontal line, which passes through a center point of the p type region, does not meet a horizontal line of the p type region that is adjacent thereto in a column direction on the plane.

12. The method of claim 11, wherein the p+ type region and the p type region respectively contact the n− type layer, and the area where the p+ type region and the n− type layer contact is wider than the area where the p type region and the n− type layer contact.

13. The method of claim 12, wherein an ion doping concentration of the p+ type region is higher than an ion doping concentration of the p type region.

14. The method of claim 13, wherein the ion doping concentration of the n type layer is higher than the ion doping concentration of the n− type layer.

15. The method of claim 14, wherein the anode includes a Schottky electrode, and the cathode includes an ohmic electrode.

16. The method of claim 15, wherein the anode includes: a first anode disposed inside the first trench and the second trench; and a second anode disposed on the first anode and the n type layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a layout showing one example of a Schottky barrier diode according to an exemplary embodiment of the present disclosure.

[0021] FIG. 2 is a cross-sectional view take along a line II-II of FIG. 1.

[0022] FIG. 3 is a layout view partially showing a Schottky barrier diode according to an exemplary embodiment of the present disclosure.

[0023] FIG. 4 is a layout view partially showing a Schottky barrier diode according to a comparative example.

[0024] FIG. 5 to FIG. 8 are views showing one example of a manufacturing method of a Schottky barrier diode according to an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. The exemplary embodiments that are disclosed herein are provided so that the disclosed contents may become thorough and complete and the spirit of the present disclosure may be sufficiently understood by a person of ordinary skill in the art.

[0026] In the drawings, the thickness of layers and regions are exaggerated for clarity. In addition, when it is mentioned that a layer is present “on” the other layer or a substrate, the layer may be directly formed on another layer or the substrate or a third layer may be interposed therebetween. Like reference numerals designate like constituent elements throughout the specification.

[0027] FIG. 1 is a layout showing one example of a Schottky barrier diode according to an exemplary embodiment of the present disclosure. FIG. 2 is a cross-sectional view take along a line II-II of FIG. 1.

[0028] As shown in FIG. 1 and FIG. 2, the Schottky barrier diode according to an exemplary embodiment includes an n+ type silicon carbide substrate 100, an n− type layer 200, an n type layer 300, a p+ type region 400, a p type region 500, an anode 600, and a cathode 700.

[0029] In the layout of FIG. 1, the n type layer 300 and the anode 600 are omitted. Referring to FIG. 1, on the plane, the p type region 500 is formed with a hexagonal shape and is separated from the p+ type region 400. The n− type layer 200 is positioned between the p type region 500 and the p+ type region 400. The n− type layer 200 positioned between the p type region 500 and the p+ type region 400 is formed with a hexagonal shape. That is, on the plane, the n− type layer 200 of the hexagonal shape encloses the p type region 500 with the hexagonal shape, and the p+ type region 400 is positioned at the remaining portion. Here, the n− type layer 200 and the p type region 500 positioned between the p type region 500 and the p+ type region 400 may have a regular hexagon shape on a plane.

[0030] The p type region 500 is in plural and is arranged in a matrix shape. The plurality of p type regions 500 are positioned in a zigzag shape in a column direction such that a horizontal line passing through a center point of the p type region 500 does not meet a horizontal line passing through the center point of the p type region 500 positioned to be adjacent thereto in the column direction on the plane.

[0031] Now, the detailed structure of the semiconductor device according to an exemplary embodiment of the present disclosure will be described.

[0032] The n− type layer 200 and the n type layer 300 are sequentially positioned at the first surface of the n+ type silicon carbide substrate 100. An ion doping concentration of the n type layer 300 may be higher than an ion doping concentration of the n− type layer 200.

[0033] The first trench 350 and the second trench 360 are formed in the n type layer 300, and the first trench 350 and the second trench 360 are adjacent to each other and are separated from each other. Depths of the first trench 350 and the second trench 360 may be the same.

[0034] The p+ type region 400 is positioned under a lower surface of the first trench 350, and the p type region 500 is positioned under the lower surface of the second trench 360. The ion doping concentration of the p+ type region 400 is higher than the ion doping concentration of the p type region 500.

[0035] The p+ type region 400 encloses a corner of the lower surface of the first trench 350 and contacts the n− type layer 200. The p type region 500 encloses the corner of the lower surface of the second trench 360 and contacts the n− type layer 200.

[0036] The anode 600 is positioned on the n type layer 300, inside the first trench 350, and inside the second trench 360. The anode 600 may include a Schottky metal. The anode 600 includes a first anode 610 positioned inside the first trench 350 and inside the second trench 360 and a second anode 620 positioned on the first anode 610 and the n type layer 300. The first anode 610 contacts the p+ type region 400 and the p type region 500.

[0037] The cathode 700 is positioned at the second surface of the n+ type silicon carbide substrate 100. The cathode 700 may include the ohmic metal. Here, the second surface of the n+ type silicon carbide substrate 100 is positioned at the side opposite to the first surface of the n+ type silicon carbide substrate 100.

[0038] Since the ion doping concentration of the p+ type region 400 is higher than the ion doping concentration of the p type region 500, when applying a foreword voltage, a hole current density in a portion where the p+ type region 400 and the n− type layer 200 are joined is higher than a hole current density in a portion where the p type region 500 and the n− type layer 200 are joined.

[0039] As described above, on the plane, the n− type layer 200 with the hexagonal shape encloses the p type region 500 with the hexagonal shape, the p+ type region 400 is positioned in the remaining portion, and the p+ type region 400 and the p type region 500 respectively contact the n− type layer 200. Accordingly, the area where the p+ type region 400 and the n− type layer 200 contact is wider than the area where the p type region 500 and the n− type layer 200 contact.

[0040] That is, the area where the p+ type region 400 and the n− type layer 200 contact is widened such that the hole current density of the Schottky barrier diode is increased, thereby increasing the entire current density of the Schottky barrier diode.

[0041] Due to the increasing of the current density of the Schottky barrier diode, the area of the Schottky barrier diode may be reduced such that the number of Schottky barrier diodes per unit wafer and the yield may be improved.

[0042] Next, a characteristic of the Schottky barrier diode according to an exemplary embodiment of the present disclosure will be described with reference to FIG. 3, FIG. 4, and Table 1.

[0043] As shown in FIG. 3 and FIG. 4, the Schottky barrier diode according to an exemplary embodiment of the present disclosure and the Schottky barrier diode according to a comparative example are prepared.

[0044] FIG. 3 is a layout view partially showing a Schottky barrier diode according to an exemplary embodiment of the present disclosure.

[0045] FIG. 4 is a layout view partially showing a Schottky barrier diode according to a comparative example.

[0046] Referring to FIG. 3, as described above, the Schottky barrier diode according to an exemplary embodiment of the present disclosure has a structure in which the n− type layer 200 of the hexagonal shape encloses the p type region 500 with the hexagonal shape and the p+ type region 400 is positioned in the remaining portion on the plane. Here, a triangle having lines respectively connecting the center of the p type region 500 and two adjacent vertices of the p type region 500 with the hexagonal shape and a line connecting center portions of two adjacent p type regions 500 as a side may be formed, and this triangle is referred to as a unit cell.

[0047] Referring to FIG. 4, the Schottky barrier diode according to a comparative example has a structure in which the p+ type region and the p type region are formed with a bar shape, and the n− type layer 200 is positioned between the p+ type region and the p type region. In this case, a quadrangle including one p type region and one p+ type region may be formed, and this quadrangle is referred to as a unit cell.

[0048] In the unit cell of the Schottky barrier diode according to an exemplary embodiment of the present disclosure, it may be confirmed that the area occupied by the p+ type region is wider than the area occupied by the p type region. In the unit cell of the Schottky barrier diode according to the comparative example, it may be confirmed that the area occupied by the p+ type region is the same as the area occupied by the p type region.

[0049] Table 1 represents a simulation result of the Schottky barrier diode according to an exemplary embodiment of the present disclosure and the Schottky barrier diode according to the comparative example when applying a foreword voltage.

TABLE-US-00001 TABLE 1 Entire Conducting Electron Hole current current portion current density density density area per unit cell per unit cell per unit cell (cm.sup.2 Division (A/μm.sup.2) (A/μm.sup.2) (A/cm.sup.2) @100 A) Comparative 124 162 286 0.350 Example Exemplary 124 203 327 0.306 Embodiment

[0050] Referring to 1, it may be confirmed that the electron current density per unit cell of the Schottky barrier diode according to the present exemplary embodiment is the same as the electron current density per unit cell of the Schottky barrier diode according to the comparative example, however, the hole current density per unit cell of the Schottky barrier diode according to the present exemplary embodiment is increased compared with the hole current density per unit cell of the Schottky barrier diode according to the comparative example by about 25%. Accordingly, it may be confirmed that the entire current density per unit cell of the Schottky barrier diode according to the present exemplary embodiment is increased compared with the entire current density per unit cell of the Schottky barrier diode according to the comparative example by about 14%.

[0051] Based on the same current amount of 100 A, it may be confirmed that the area of the Schottky barrier diode according to the present exemplary embodiment is decreased compared with the area of the Schottky barrier diode according to the comparative example by about 13%. Therefore, a greater number of Schottky barrier diodes according to the present exemplary embodiment may be included per unit wafer compared with the Schottky barrier diodes according to the comparative example, thereby reducing the cost.

[0052] Next, a manufacturing method of a semiconductor element according to an exemplary embodiment of the present disclosure will be described with reference to FIG. 5 to FIG. 8.

[0053] FIG. 5 to FIG. 8 are views showing one example of a manufacturing method of a Schottky barrier diode according to an exemplary embodiment of the present disclosure.

[0054] Referring to FIG. 5, an n+ type silicon carbide substrate 100 is prepared, and an n− type layer 200 and an n type layer 300 are sequentially formed at a first surface of the n+ type silicon carbide substrate 100. The ion doping concentration of the n type layer 300 may be higher than the ion doping concentration of the n− type layer 200.

[0055] Here, the n− type layer 200 is formed by epitaxial growth at the first surface of the n+ type silicon carbide substrate 100, and the n type layer 300 is formed is formed by epitaxial growth on the n− type layer 200.

[0056] The n− type layer 200 is formed by epitaxial growth at the first surface of the n+ type silicon carbide substrate 100, and the n type layer 300 may be formed by injecting the n type ion at the surface of the n− type layer 200.

[0057] Referring to FIG. 6, the n type layer 300 is etched to form a first trench 350 and a second trench 360. The first trench 350 and the second trench 360 are adjacent to and separated from each other. The depth of the first trench 350 and the second trench 360 may be the same.

[0058] Referring to FIG. 7, the p+ type ion is injected to a lower surface of the first trench 350 to form the p+ type region 400. The p+ type region 400 is formed under the lower surface of the first trench 350, encloses the corner of the lower surface of the first trench 350, and contacts the n− type layer 200.

[0059] Referring to FIG. 8, the p type ion is injected to the lower surface of the second trench 360 to form the p type region 500. The p type region 500 is formed under the lower surface of the second trench 360, encloses the lower surface of the second trench 360, and contacts the n− type layer 200. Here, the ion doping concentration of the p type region 500 is lower than the ion doping concentration of the p+ type region 400.

[0060] Next, as shown in FIG. 1, on the plane, the p type region 500 has the hexagonal shape and is separated from the p+ type region 400, and the n− type layer 200 is positioned between the p type region 500 and the p+ type region 400. The n− type layer 200 positioned between the p type region 500 and the p+ type region 400 has the hexagonal shape. That is, on the plane, the n− type layer 200 of the hexagonal shape encloses the p type region 500 of the hexagonal shape, and the p+ type region 400 is positioned at the remaining portion.

[0061] The p type region 500 is in plural and is positioned in the matrix shape. The plurality of p type regions 500 are positioned with the zigzag shape in the column direction such that the horizontal line passing through the center point of the p type region 500 does not meet the horizontal line passing through the p type region 500 positioned to be adjacent to each other in the column direction on the plane.

[0062] Referring to FIG. 2, the anode 600 is formed on the n type layer 300, inside the first trench 350, and inside the second trench 360, and the cathode 700 is formed at the second surface of the n+ type silicon carbide substrate 100.

[0063] Here, the anode 600 includes a first anode 610 positioned inside the first trench 350 and the second trench 360 and a second anode 620 positioned on the first anode 610 and the n type layer 300. The first anode 610 contacts the p+ type region 400 and the p type region 500.

[0064] The anode 600 may include the Schottky metal, and the cathode 700 may include the ohmic metal.

[0065] On the other hand, in the manufacturing method of the semiconductor element according to the present exemplary embodiment, the p+ type region 400 and the p type region 500 are formed after simultaneously forming the first trench 350 and the second trench 360, however it is not limited thereto, and the first trench 350 may be firstly formed, and the p+ type region 400 may be formed under the lower surface of the first trench 350 and then the second trench 360 may be formed and the p type region 500 may be formed under the lower surface of the second trench 360.

[0066] While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.