Disclosed is a manufacturing method of a trench-type power device. The manufacturing method comprises: forming a drift region; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming a doped region and a well region of P type in the drift region by performing first ion implantation; forming a source region of N type in the well region by performing second ion implantation. The well region in which a dopant concentration gradually decreases with depth is formed by the first ion implantation, an upper part of the well region is inverted by the second ion implantation to form the source region. The doped region and well region can be formed by self-alignment in a common ion implantation step, improving power device performance, reducing numbers of process steps of ion implantation and masks, reducing manufacturing cost.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.

A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.

First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.

A metal layer is deposited on a wafer that has silicon carbide, wherein the metal layer forms a contact face. A laser annealing is performed at the contact face using a laser beam application that causes the metal layer to react with the wafer and form a silicide layer. The laser beam has a footprint having a size. To laser anneal the contact face, a first portion of the contact face is irradiated, the footprint of the laser beam is moved by a step smaller than the size of the footprint, and a second portion of the contact face is irradiated, thereby causing the first portion and the second portion of the contact face to overlap.

A SiC semiconductor device includes a main cell region and sense cell region being electrically isolated by an element isolation portion. The SiC semiconductor device includes a substrate, a first impurity region, a first current dispersion layer, first deep layers, a second current dispersion layer, a second deep layer, a base region, a trench gate structure, a second impurity region, first electrodes and a second electrode. The second impurity region, the first electrodes, and the second electrode are disposed at the main cell region and the sense cell region to form a vertical semiconductor element. The vertical semiconductor element allows a current flowing between the first electrode and the second electrode through a voltage applied to the gate electrode. The spacing interval between the deep layers at the element isolation portion is shorter than or equal to a spacing interval between the deep layers at the main cell region.