The present invention is an IC chip mounting apparatus for mounting an IC chip at a reference position of an inlay antenna while conveying the antenna, the IC chip mounting apparatus including: a nozzle configured to suck an IC chip when located at a first position and to place the IC chip at the reference position of the antenna when located at a second position; a nozzle attachment to which the nozzle is attached; an image acquisition unit configured to acquire an image of the IC chip sucked by the nozzle; and a correction amount determination unit configured to determine correction amounts for the IC chip sucked by the nozzle, based on the image acquired by the image acquisition unit. The correction amounts includes a first correction amount for correcting an angle of the nozzle around the axis, a second correction amount for correcting a position of the antenna in a conveying direction of the antenna, and a third correction amount for correcting the position of the antenna in a width direction.

A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

Metrology is performed on a semiconductor wafer using a system with an apodizer. A spot is formed on the semiconductor wafer with a diameter from 2 nm to 5 nm. The associated beam of light has a wavelength from 400 nm to 800 nm. Small target measurement can be performed at a range of optical wavelengths.

Systems and methods for determining a diagnosis of a screening system are disclosed. Such systems and methods include identifying defect results based on inline characterization tool data, identifying electrical test results based on electrical test data, generating one or more correlation metrics based on the defect results and the electrical test results, and determining at least one diagnosis of the screening system based on the one or more correlation metrics, the diagnosis corresponding to a performance of the screening system.

A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

Methods and apparatus for processing a first substrate and a second substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a first surface of a first substrate and a second surface of a second substrate, which is different than the first substrate, determining in-situ ESE data from each of the first surface and the second surface during processing of the first substrate and the second substrate, measuring a change of phase and amplitude in determined in-situ ESE data, and determining one or more parameters of the first surface of the first substrate and the second surface of the second substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from the measured change of phase and amplitude in the in-situ ESE data.

A defect observation method includes, as steps executed by a computer system, a first step of acquiring, as a bevel image, an image captured using defect candidate coordinates in a bevel portion as an imaging position by using a microscope or an imaging apparatus; and a second step of detecting a defect in the bevel image. The second step includes a step of determining whether there is at least one portion among a wafer edge, a wafer notch, and an orientation flat in the bevel image, a step of switching and selectively applying a defect detection scheme of detecting the defect from the bevel image from a plurality of schemes which are candidates based on a determination result, and a step of executing a process of detecting the defect from the bevel image in conformity with the switched scheme.

A data processing device for detecting defects in sample image data generated by a charged particle assessment system, the device comprising: a first processing module configured to receive a sample image datastream from the charged particle assessment system, the sample image datastream comprising an ordered series of data points representing an image of the sample, and to apply a first defect detection test to select a subset of the sample image datastream as first selected data, wherein the first defect detection test is a localised test which is performed in parallel with receipt of the sample image datastream; and a second processing module configured to receive the first selected data and to apply a second defect detection test to select a subset of the first selected data as second selected data.