Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

A system for monitoring one or more conditions of an automation system of a semiconductor factory includes one or more instrumented substrates, one or more sealable containers and one or more system servers. The one or more instrumented substrates include one or more sensors. The one or more sensors measure one or more conditions of the one or more instrumented substrates as the one or more sealable containers transport the one or more instrumented substrates through the semiconductor factory. The one or more sealable containers also receive sensor data from the one or more sensors included on the one or more instrumented substrates. The one or more system servers are configured to receive the sensor data from the one or more sealable containers. The one or more servers are configured to identify one or more deviations in the measured one or more conditions.

A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

A thermal processing system for performing thermal processing can include a workpiece support plate configured to support a workpiece and heat source(s) configured to heat the workpiece. The thermal processing system can include window(s) having transparent region(s) that are transparent to electromagnetic radiation within a measurement wavelength range and opaque region(s) that are opaque to electromagnetic radiation within a portion of the measurement wavelength range. A temperature measurement system can include a plurality of infrared emitters configured to emit infrared radiation and a plurality of infrared sensors configured to measure infrared radiation within the measurement wavelength range where the transparent region(s) are at least partially within a field of view the infrared sensors. A controller can be configured to perform operations including obtaining transmittance and reflectance measurements associated with the workpiece and determining, based on the measurements, a temperature of the workpiece less than about 600° C.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.

A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.

A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

A method for measuring a resistance value of a contact plug is provided. The method includes: providing a structure to be tested, and the structure to be tested including: a plurality of transistors disposed on a substrate in sequence, each transistor including a gate and source-drain doping regions on the substrate and located at two sides of the gate, and two adjacent source-drain doping regions are electrically connected; and a plurality of contact plugs disposed on the substrate in sequence, each transistor being located between two adjacent contact plugs, and bottoms of the contact plugs being electrically connected to the source-drain doping regions; selecting at least two units to be tested from the structure to be tested; obtaining resistance values of respective units to be tested by performing measurement; and determining the resistance value of the contact plug based on the resistance values of the respective unit to be tested.