Patent classifications
H01L23/06
Current introduction terminal, and pressure holding apparatus and X-ray image sensing apparatus therewith
A current introduction terminal includes a board made of resin. The board has a first face and a second face opposite each other. The board hermetically separates environments of different air pressures from each other. A plurality of through via holes corresponding both to a plurality of metal terminals of a first surface-mount connector to be mounted on the first face and to a plurality of metal terminals of a second surface-mount connector to be mounted on the second face are formed to penetrate between the first and second faces, and then hole parts of the through via holes are filled with resin.
Package Structure for Semiconductor Device and Preparation Method Thereof
This disclosure provides a package structure for a semiconductor device, comprising a three-layer film consisting of a first SiO.sub.2 film, a Si.sub.3N.sub.4 film and a second SiO.sub.2 film stacked in this order, wherein the first SiO.sub.2 film is formed by a thermal oxidation process, the Si.sub.3N.sub.4 film is formed by a low pressure chemical vapor deposition process, and the second SiO.sub.2 film is formed by a low temperature atomic layer deposition process. This disclosure also provides a method for preparing the package structure for a semiconductor device.
Package Structure for Semiconductor Device and Preparation Method Thereof
This disclosure provides a package structure for a semiconductor device, comprising a three-layer film consisting of a first SiO.sub.2 film, a Si.sub.3N.sub.4 film and a second SiO.sub.2 film stacked in this order, wherein the first SiO.sub.2 film is formed by a thermal oxidation process, the Si.sub.3N.sub.4 film is formed by a low pressure chemical vapor deposition process, and the second SiO.sub.2 film is formed by a low temperature atomic layer deposition process. This disclosure also provides a method for preparing the package structure for a semiconductor device.
POWER DEVICE ASSEMBLIES AND COOLING DEVICES FOR COOLING HEAT- GENERATING DEVICES
A power device assembly includes a heat-generating device, one or more porous bonding layers, and one or more cap layers. The one or more porous bonding layers are formed on a surface of the heat-generating device and define a plurality of embedded vapor channels. The one or more cap layers are engaged with a porous bonding layer of the one or more porous bonding layers opposite the heat-generating device. The one or more cap layer comprise a plurality of liquid feed channels for feeding cooling fluid to the heat-generating device via the porous bonding layer.
POWER DEVICE ASSEMBLIES AND COOLING DEVICES FOR COOLING HEAT- GENERATING DEVICES
A power device assembly includes a heat-generating device, one or more porous bonding layers, and one or more cap layers. The one or more porous bonding layers are formed on a surface of the heat-generating device and define a plurality of embedded vapor channels. The one or more cap layers are engaged with a porous bonding layer of the one or more porous bonding layers opposite the heat-generating device. The one or more cap layer comprise a plurality of liquid feed channels for feeding cooling fluid to the heat-generating device via the porous bonding layer.
Semiconductor package structure and methods of manufacturing the same
The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.
SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY
A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, a metal ring is provided that conforms to or is congruent to a shape of a lower lip of the lid. A dielectric material covers the metal ring, and a low modulus epoxy is used to bind the lower lip of the lid to the dielectric material. The lid and metal ring may have comparable thermal coefficients, which, when coupled with the low modulus epoxy, reduces chance of gross failure of the cavity.
SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY
A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, a metal ring is provided that conforms to or is congruent to a shape of a lower lip of the lid. A dielectric material covers the metal ring, and a low modulus epoxy is used to bind the lower lip of the lid to the dielectric material. The lid and metal ring may have comparable thermal coefficients, which, when coupled with the low modulus epoxy, reduces chance of gross failure of the cavity.
INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.