Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

A vacuum cell including a vacuum chamber, a first bond, and a second bond is described. The first bond affixes a first portion of the vacuum cell to a second portion of the vacuum cell. The first bond has a first bonding temperature and a first debonding temperature greater than the first bonding temperature. The second bond affixes a third portion of the vacuum cell to a fourth portion of the vacuum cell. The second bond has a second bonding temperature and a second debonding temperature. The second bonding temperature is less than the first debonding temperature.

An outer frame (outer wall) of a housing of a semiconductor device has a spacer portion that protrudes beyond a bottom surface of a cooling bottom plate in an opposite direction to a semiconductor chip. When the semiconductor device is placed on an arbitrary placement surface for example, the spacer portion produces a gap between a rear surface of a cooling device (that is, a bottom surface of the cooling bottom plate) and the placement surface. This means that the bottom surface of the cooling bottom plate does not directly touch the placement surface and is less likely to be damaged. Favorable sealing is maintained between pipes, which are attached to the cooling device of the semiconductor device, and an inlet and an outlet on the cooling bottom plate.

An outer frame (outer wall) of a housing of a semiconductor device has a spacer portion that protrudes beyond a bottom surface of a cooling bottom plate in an opposite direction to a semiconductor chip. When the semiconductor device is placed on an arbitrary placement surface for example, the spacer portion produces a gap between a rear surface of a cooling device (that is, a bottom surface of the cooling bottom plate) and the placement surface. This means that the bottom surface of the cooling bottom plate does not directly touch the placement surface and is less likely to be damaged. Favorable sealing is maintained between pipes, which are attached to the cooling device of the semiconductor device, and an inlet and an outlet on the cooling bottom plate.

A camera module and photosensitive component or unit thereof and manufacturing method therefor are provided. The photosensitive unit includes an encapsulation portion and a photosensitive portion that includes a main circuit board and a photosensitive sensor, wherein the encapsulation portion is integrally encapsulated to form on the main circuit board and the photosensitive sensor.

A camera module and photosensitive component or unit thereof and manufacturing method therefor are provided. The photosensitive unit includes an encapsulation portion and a photosensitive portion that includes a main circuit board and a photosensitive sensor, wherein the encapsulation portion is integrally encapsulated to form on the main circuit board and the photosensitive sensor.

A method for producing singulated encapsulated components. The method includes the steps of application of a frame structure on a substrate surface of a substrate, wherein the frame structure surrounds components arranged on the substrate surface; bonding of a cover substrate on the frame structure; hardening of the frame structure; and singulation of the encapsulated components, wherein the frame structure is formed from an adhesive.

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

An electronic component includes a mounting substrate, and first and second devices each including a functional element. The first device is spaced apart from and faces the mounting substrate. The second device is located on the mounting substrate and faces the first device. A functional element of the first device is located on a first surface facing the second device, in the first device. A functional element of the second device is located on a second surface facing the first device, in the second device.

An electronic component includes a mounting substrate, and first and second devices each including a functional element. The first device is spaced apart from and faces the mounting substrate. The second device is located on the mounting substrate and faces the first device. A functional element of the first device is located on a first surface facing the second device, in the first device. A functional element of the second device is located on a second surface facing the first device, in the second device.