Patent classifications
H01L23/10
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
In one example, an electronic device comprises a cavity substrate comprising a substrate base comprising a top side and a bottom side and a cavity wall over the substrate base and defining a cavity, an electronic component over the substrate base and in the cavity, a lid comprising a top side and a bottom side, wherein the lid is over the substrate base and the cavity wall to define an interior of the cavity and an exterior of the cavity, an adhesive between the bottom side of the lid and a top side of the cavity wall, and a vent seal between the interior of the cavity and the exterior of the cavity. Other examples and related methods are also disclosed herein.
Immersion plating treatments for indium passivation
A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.
LID, ELECTRONIC COMPONENT-HOUSING PACKAGE, AND ELECTRONIC DEVICE
Provided is a lid of an electronic component-housing package. The lid includes a conductor layer and a dielectric layer. The conductor layer includes at least one opening and a first part surrounding the at least one opening. The dielectric layer includes a second part, a first dielectric layer, and a second dielectric layer. The second part is located in the at least one opening. The first dielectric layer lies on the top of the conductor layer. The second part lies on the underside of the conductor layer.
PACKAGE ASSEMBLY INCLUDING LIQUID ALLOY THERMAL INTERFACE MATERIAL AND METHODS OF FORMING THE SAME
A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.
PACKAGE ASSEMBLY INCLUDING LIQUID ALLOY THERMAL INTERFACE MATERIAL AND METHODS OF FORMING THE SAME
A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.
Double-sided hermetic multichip module
A packaged electronic module for downhole applications, in particular in a petrochemical well or similar environment. The electronic module includes one or more electronic components located on each side of a substrate, where the one or more electronic components are attached to the substrate by means of glue.
Double-sided hermetic multichip module
A packaged electronic module for downhole applications, in particular in a petrochemical well or similar environment. The electronic module includes one or more electronic components located on each side of a substrate, where the one or more electronic components are attached to the substrate by means of glue.
Semiconductor module
A semiconductor module includes a power element, a signal wiring, and a heat sink. The signal wiring is connected to a signal pad of the power element. The heat sink cools the power element. The power element has an active area provided by a portion where the signal pad is formed. The signal pad is thermally connected to the heat sink via the signal wiring.
Molded air-cavity package and device comprising the same
The present invention relates to a molded air-cavity package. In addition, the present invention is related to a device comprising the same. The present invention is particularly related to molded air-cavity packages for radio-frequency ‘RF’ applications including but not limited to RF power amplifiers. Instead of using hard-stop features that are arranged around the entire perimeter of the package in a continuous manner, the present invention proposes to use spaced apart pillars formed by first and second cover supporting elements. By using only a limited amount of pillars, e.g. three or four, the position of the cover relative to the body can be defined in a more predictable manner. This particularly holds if the pillars are arranged in the outer corners of the package.
BOND FOOT SEALING FOR CHIP FRONTSIDE METALLIZATION
A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.