A semiconductor device of an embodiment includes: a wiring board; a semiconductor chip mounted on the wiring board; and a resin-containing layer bonded on the wiring board so as to fix the semiconductor chip to the wiring board. The resin-containing layer contains a resin-containing material having a breaking strength of 15 MPa or more at 125° C.

A method for forming a semiconductor structure includes curing a shape memory polymer in a first shape. The shape memory polymer is coupled to a conductive layer. The method further includes folding the shape memory polymer from the first shape into a second shape. The method also includes bonding a semiconductor wafer to the conductive layer while the shape memory polymer is in the second shape. The semiconductor wafer has first and second dies. The semiconductor wafer is then singulated to separate the first die from the second die. The method further includes expanding the shape memory polymer to its first shape and singulating the shape memory polymer to separate the first and second dies.

A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

Alignment accuracy between an imaging element and a filming lens is improved. An imaging apparatus includes an imaging element, a wiring substrate, a sealing section, and fitting sections. The imaging element includes an imaging chip and pads. A light transmission section that transmits incident light is arranged on the imaging chip, and the imaging chip generates an image signal on the basis of the incident light that has transmitted through the light transmission section. The pads are arranged on a bottom surface of the imaging chip which is a surface different from the surface on which the light transmission section is arranged and convey the generated image signal. The wiring substrate includes wiring that is connected to the pads, and the imaging element is arranged on a front surface of the wiring substrate. The sealing section is arranged adjacent to side surfaces of the imaging chip which are the surfaces adjacent to the bottom surface of the imaging chip and seals the imaging chip. The fitting sections are arranged in the sealing section, and part of a lens unit for forming an optical image on the imaging element is fitted into the fitting sections.

Alignment accuracy between an imaging element and a filming lens is improved. An imaging apparatus includes an imaging element, a wiring substrate, a sealing section, and fitting sections. The imaging element includes an imaging chip and pads. A light transmission section that transmits incident light is arranged on the imaging chip, and the imaging chip generates an image signal on the basis of the incident light that has transmitted through the light transmission section. The pads are arranged on a bottom surface of the imaging chip which is a surface different from the surface on which the light transmission section is arranged and convey the generated image signal. The wiring substrate includes wiring that is connected to the pads, and the imaging element is arranged on a front surface of the wiring substrate. The sealing section is arranged adjacent to side surfaces of the imaging chip which are the surfaces adjacent to the bottom surface of the imaging chip and seals the imaging chip. The fitting sections are arranged in the sealing section, and part of a lens unit for forming an optical image on the imaging element is fitted into the fitting sections.

A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions. Methods of producing the power semiconductor module and power electronic assemblies that incorporate the power semiconductor module are also described.

Various disclosed embodiments include a substrate, a first interposer coupled to the substrate and to a first semiconductor device die, and a second interposer coupled to the substrate and to a second semiconductor device die. The first semiconductor device die may be a serializer/de-serializer die and the first semiconductor device die coupled to the first interposer may be located proximate to a sidewall of the substrate. In certain embodiments, the second semiconductor device die may be a system-on-chip die. In further embodiments, the second interposer may also be coupled to high bandwidth memory die. Placing a serializer/de-serializer die proximate to a sidewall of a substrate allows a length of electrical pathways to be reduced, thus reducing impedance and RC delay. The use of smaller, separate, interposers also reduces complexity of fabrication of interposers and similarly lowers impedance associated with redistribution interconnect structures associated with the interposers.

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.