A display device and a chip-on-film structure thereof are provided. The chip-on-film structure includes a substrate, multiple first output pads, multiple second output pads, multiple first lead wires, and multiple second lead wires. The substrate has a surface including a bonding zone. The first and output pads are located in the bonding zone. The first lead wires and the first output pads are located on the same surface of the substrate. The first lead wires and the second lead wires are located on two opposite surfaces of the substrate. Each of the first lead wires is connected to one of the first output pads. Each of the second lead wires is connected to one of the second output pads. The second lead wires each have a portion corresponding to the bonding zone and having the terminal sections that are respectively opposite to the first and second output pads.

An integrated circuit (IC) package, comprising a die having a first set of interconnects of a first pitch, and an interposer comprising an organic substrate having a second set of interconnects of a second pitch. The interposer also includes an inorganic layer over the organic substrate. The inorganic layer comprises conductive traces electrically coupling the second set of interconnects with the first set of interconnects. The die is attached to the interposer by the first set of interconnects. In some embodiments, the interposer further comprises an embedded die. The IC package further comprises a package support having a third set of interconnects of a third pitch, and a second inorganic layer over a surface of the interposer opposite to the die. The second inorganic layer comprises conductive traces electrically coupling the third set of interconnects with the second set of interconnects.

An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.

A semiconductor device comprises; a lead frame having leads and a die pad; a printed circuit board including an electrode for the connection of each of the leads and the die pad, a wiring pattern, and an opening exposing a part of a surface of the die pad; the semiconductor element for processing a high frequency signal, mounted on a surface of a metal block bonded to the surface of the die pad exposed through the opening, and connected to the wiring pattern with a metal wire; electronic components connected to the wiring pattern and mounted on a surface of the printed circuit board; and a sealing resin to seal the printed circuit board, the semiconductor element, the electronic components, and the metal wire so as to expose rear surfaces of the leads and the die pad.

A wiring base includes an insulation base having a first surface, a first differential-wiring channel, and a second differential-wiring channel. The first and the second differential-wiring channels are on the first surface and arranged side by side in a first direction. The first differential-wiring channel includes a pair of first signal conductors extending in a second direction intersecting the first direction and a pair of first grounding conductors extending along the first signal conductors with the first signal conductors being interposed therebetween. The second differential-wiring channel includes a pair of second signal conductors extending in the second direction and a pair of second grounding conductors extending along the second signal conductors with the second signal conductors being interposed therebetween. The wiring base further includes a first film extending in the second direction and positioned between first and second grounding conductors adjacent to each other in plan of the first surface.

Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.

The present invention relates to a maleimide resin composition including (A) at least one selected from the group consisting of a maleimide compound having two or more N-substituted maleimide groups and a derivative thereof; and (B) a modified conjugated diene polymer, the component (B) being one resulting from modification of (b1) a conjugated diene polymer having a vinyl group in the side chain with (b2) a maleimide compound having two or more N-substituted maleimide groups and also to a prepreg, a laminate, a resin film, a multilayer printed wiring board, and a semiconductor package, each using the foregoing maleimide resin composition.

A semiconductor device, including an insulated circuit substrate that has a base plate, a resin layer disposed on a front surface of the base plate, and a circuit pattern disposed on a front surface of the resin layer; and a semiconductor chip that is rectangular in a plan view of the semiconductor device and is bonded to a front surface of the circuit pattern in such a manner that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by at least a predetermined distance. Both the predetermined distance and a thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip.

An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.

A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.