A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

A semiconductor device for testing a semiconductor wafer includes a circuit board, a probe disposed below the circuit board and facing the semiconductor wafer, an integrated substrate disposed between the circuit board and the probe, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The probe is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the probe through the integrated substrate and the circuit board to perform a test to the semiconductor wafer. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

Provided is a curable resin composition for obtaining a cured product that can satisfy both high heat resistance and high adhesiveness to metal, a cured product thereof, and methods of producing the curable resin composition and the cured product, and a semiconductor device using the cured product as a sealant. A curable resin composition containing (A) a multifunctional benzoxazine compound having two or more benzoxazine rings, (B) a multifunctional epoxy compound having at least one norbornane structure and at least two epoxy groups, (C) a curing agent, (D) a triazole-based compound, and optionally (E) a curing accelerator and (F) an inorganic filler, a cured product thereof, and methods of producing the curable resin composition and the cured product. A semiconductor device in which a semiconductor element is disposed in a cured product obtained by curing a curable resin composition containing components (A) to (D), and optionally components (E) and (F).

A tablet form of an epoxy resin composition for encapsulation of semiconductor elements, where the tablet form of the epoxy resin composition: (i) includes 97 wt % or more of tablets having a diameter of 0.1 mm to less than 2.8 mm and a height of 0.1 mm to less than 2.8 mm, as measured using an ASTM standard sieve; (ii) satisfies the following Equation 1, $\frac{\sigma D\times \sigma H}{\sigma D+\sigma H}\le 1.0,$
where σD is a standard deviation of tablet diameters and σH is a standard deviation of tablet heights, as measured with respect to 50 tablets arbitrarily selected from the tablets; and (iii) the tablets have a compression density of 1.2 g/mL to 1.7 g/mL.

The present invention relates to an epoxy resin composition for molding a semiconductor having excellent heat resistance and mechanical properties and also having improved visibility while having a low coefficient of thermal expansion and thus exhibiting improved warpage characteristics, and a molding film and a semiconductor package using such an epoxy resin composition for molding a semiconductor.

A universal implantable integrated circuit medical device platform having integral and monolithic circuit traces. The platform allows for implanting into a mammalian body single and multi-functional interface devices for sensing, monitoring stimulating and/or modulating physiological conditions within the body. Microelectronic circuitry may be integrated onto the platform or may be joined as modular components to the platform.

A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided.