CHIP-SCALE PACKAGE

Abstract

A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Claims

1. A method for manufacturing a semiconductor device, the device being a chip-scale package, comprising: providing a plurality of semiconductor dies arranged on a carrier, wherein the semiconductor dies have a first surface by which they are arranged on the carrier and a second surface opposite to the first surface, wherein the semiconductor dies each comprise an inner part and a perimeter part surrounding the inner part, wherein the semiconductor dies each comprise, in the perimeter part, at least a remainder of a sawing line or dicing street that was or is to be used for singulating the semiconductor dies from other semiconductor dies on a semiconductor wafer, and a semiconductor vertical device realized inside the inner part, wherein in at least the inner parts of the semiconductor dies a passivation layer is arranged, wherein each semiconductor die comprises at least one first terminal arranged at its first surface, at least one second terminal that is arranged at its second surface in its inner part and that is at least partially exposed through one or more openings in the passivation layer, and sidewalls extending between the first and second surfaces, wherein at the second surfaces of the semiconductor dies a sacrificial layer is provided, wherein the sacrificial layer at least partially covers the at least one second terminal, and comprises first openings aligned with spaces between adjacent semiconductor dies, and second openings at least partially aligned with the perimeter parts of the second surfaces of the semiconductor dies; arranging a conformal coating on the semiconductor dies; and removing the conformal coating arranged on the sacrificial layer by removing the sacrificial layer; wherein the conformal coating that has remained on the semiconductor dies covers the perimeter parts of the semiconductor dies and covers the sidewalls of the semiconductor dies at least partially.

2. The method according to claim 1, wherein the conformal coating that has remained on the semiconductor dies at least partially covers the inner parts of the semiconductor dies, and wherein the conformal coating comprises one or more openings through which the at least one second terminals are at least partially exposed.

3. The method according to claim 2, wherein the conformal coating that has remained on the semiconductor dies at least partially covers the passivation layer.

4. The method according to claim 3, wherein the one or more openings in the conformal coating that has remained on the semiconductor dies are aligned with the one or more openings in the passivation layer for the purpose of exposing the at least one second terminals.

5. The method according to claim 1, wherein the perimeter parts are not or not fully covered by the passivation layer.

6. The device according to previous claim 1, wherein the passivation layer is one or more of the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.

7. The method according to claim 1, wherein the plurality of semiconductor dies corresponds to a diced semiconductor wafer arranged on the carrier, wherein the diced wafer corresponds to a partially-cut diced wafer, in which the dies are still interconnected through a part of the semiconductor wafer, or wherein the diced wafer corresponds to a full-cut diced wafer in which the semiconductor dies have been physically separated.

8. The method according to claim 1, wherein the arranging a conformal coating comprises performing atomic layer deposition, and wherein the performing atomic layer deposition comprises using trimethylaluminum and water, and titanium tetrachloride and water as precursor pairs.

9. The method according to claim 1, wherein the providing a plurality of semiconductor dies comprises arranging the sacrificial layer on the semiconductor dies while still being interconnected in a wafer before dicing; and wherein the providing a plurality of semiconductor dies comprises arranging the sacrificial layer on the second surface of the semiconductor dies while still being interconnected in a wafer and before arranging this wafer on the carrier.

10. The method according to claim 9, wherein the arranging the sacrificial layer on the second surface of the semiconductor dies comprises depositing a layer on the second surface, the layer being chosen from the group consisting of photoresist, polymers, thin metal layers, self-assembled monolayers, and combinations thereof.

11. The method according to claim 10, further comprising arranging and patterning a masking layer on the sacrificial layer and removing the sacrificial layer through openings in the masking layer.

12. The method according to claim 1, wherein the second terminals are formed using a metal layer stack comprising a plurality of metal layers, wherein the sacrificial layer is formed by one or more metal layers that are arranged farthest from the second surface or a part thereof, and wherein the metal layer stack comprises TiNiVAg, NiAu, Ni, Al, TiNiAg, AuNiAg, AuAsNiAg, and any combinations thereof.

13. The method according to claim 1, wherein the removing the sacrificial layer comprises ablating the sacrificial layer by photo-ablation.

14. The method according to claim 1, wherein the removing the sacrificial layer comprises: providing a thermal shock to the sacrificial layer and conformal coating causing the conformal coating and sacrificial layer to mutually delaminate; and removing the delaminated conformal coating; wherein the sacrificial layer is a photo-sensitive layer that is a photoresist, and wherein the thermal shock is provided by applying optical energy; the method further comprising performing a cleaning step for removing the remaining sacrificial layer.

15. The method according to claim 1, wherein the removing the sacrificial layer comprises performing a grinding, dicing, cutting or other mechanical operation for removing the sacrificial layer and the conformal coating covering that layer by physically engaging the conformal coating and sacrificial layer, the method further comprising performing a cleaning step for removing the remaining sacrificial layer.

16. The method according to claim 1, wherein the providing a plurality of semiconductor dies comprises attaching a first foil as the sacrificial layer to the second surface of the semiconductor dies, wherein the first foil is provided with the first and second openings, and wherein the removing the sacrificial layer comprises removing the first foil from the second surface.

17. The method according to claim 1, wherein the carrier comprises a second foil, wherein the second foil is a dicing foil, and/or wherein the second foil comprises a plurality of openings to allow the conformal coating to be formed on the sidewalls through the openings.

18. A semiconductor device, being a chip-scale package, comprising a semiconductor die, the semiconductor die comprising: an inner part and a perimeter part surrounding the inner part, wherein the semiconductor die comprises, in the perimeter part, at least a remainder of a sawing line or dicing street that was used for singulating the semiconductor die from other semiconductor dies on a semiconductor wafer, and a semiconductor vertical device realized inside the inner part; a passivation layer arranged in at least the inner part of the semiconductor die; a first surface, and a second surface opposite to the first surface, wherein the semiconductor die comprises at least one first terminal arranged at its first surface, at least one second terminal that is arranged at its second surface and that is at least partially exposed through one or more openings in the passivation layer, and sidewalls extending between the first and second surfaces; a conformal coating covering the perimeter part and at least a part of the sidewalls to prevent a short-circuit from occurring between the at least one first and the at least one second terminals when mounting the device on a carrier.

19. The device according to claim 18, wherein the conformal coating at least partially covers the inner part of the first surface, the conformal coating comprising one or more openings through which the at least one second terminal is at least partially exposed.

20. The device according to claim 19, wherein the conformal coating at least partially covers the passivation layer.

21. The device according to claim 20, wherein the one or more openings in the conformal coating are aligned with the one or more openings in the passivation layer for the purpose of exposing the at least one second terminal.

22. The device according to claim 18, wherein the perimeter part is not, or not fully, covered by the passivation layer.

23. The device according to claim 18, wherein the passivation is at least one of the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.

24. The device according to claim 18, wherein the at least one second terminal is provided with a plurality of islands comprising the conformal coating.

25. The device according to claim 18, the conformal coating comprises a coating obtained by atomic layer deposition.

26. The device according to claim 25, wherein the conformal coating comprises an alternating arrangement of Al.sub.2O.sub.3 and TiO.sub.2 layers.

27. The device according to claim 18, wherein the vertical device is a device chosen from the group consisting of trench MOSFETs, planar MOSFETs, PN diodes, Schottky diodes, Zener diodes, and bipolar junction transistors, and/or wherein the semiconductor die comprises a conductive semiconductor substrate, being an n-type or p-type doped semiconductor substrate.

28. The device according to claim 18, wherein the device comprises a normal direction that extends perpendicular to and from the first surface to the second surface, wherein the device is configured to be arranged on a carrier, that is a printed circuit board, with its normal direction parallel to the carrier, wherein the at least one first terminal is configured to be connected to at least one first contact pad on the carrier, and wherein the at least one second terminal is configured to be connected to at least one second contact pad on the carrier.

29. A system, comprising: a carrier, that is a printed circuit board, comprising at least one first contact pad and at least one second contact pad spaced apart from the at least one first contact pad; the semiconductor device according to claim 28, mounted to the carrier with its normal direction parallel to the carrier; wherein the at least one first terminal is electrically connected to the at least one first contact pad using electrically conductive attaching material; and wherein the at least one second terminal is electrically connected to the at least one second contact pad using electrically conductive attaching material.

30. The system according to claim 29, wherein the electrically conductive attaching material is one or more of the group consisting of solder, conductive glue, and silver sinter material.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0051] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0052] FIG. 1 illustrates a known chip-scale package.

[0053] FIG. 2 illustrates mounting the chip-scale package.

[0054] FIG. 3 illustrates a known chip-scale package that is mounted to a carrier illustrating the problem of a short-circuit occurring between a device terminal and a sidewall of the semiconductor die of the chip-scale package.

[0055] FIG. 4 illustrates a chip-scale package in accordance with an aspect of the present disclosure that is mounted to a carrier.

[0056] FIGS. 5A and 5B schematically illustrate two different embodiments of a chip-scale package in accordance with an aspect of the present disclosure.

[0057] FIGS. 6, 7, 8 and 9 illustrate four methods for manufacturing a chip-scale package in accordance with various aspects of the present disclosure.

[0058] FIG. 10 illustrates various configurations for openings in the passivation layer and conformal coating in accordance with various aspects of the present disclosure.

DETAILED DESCRIPTION

[0059] FIG. 4 illustrates a chip-scale package that is mounted to a carrier in accordance with an aspect of the present disclosure. Compared to the chip-scale package shown in FIG. 3, it can be observed that sidewalls of semiconductor die 1 are now covered by a conformal coating as indicated by the hashing, while terminals T1 and T3 are not covered by this coating. A more detailed explanation on this and other chip-scale packages will be provided referring to FIGS. 5A and 5B that schematically illustrate two different embodiments of a chip-scale package in accordance with an aspect of the present disclosure.

[0060] FIG. 5A illustrates an embodiment of a three-terminal chip-scale package 20A in accordance with an aspect of the present disclosure. Package 20A comprises a semiconductor die 22 having a first surface at which terminals T1, T3 are arranged, and a second surface at which a terminal T2 is arranged.

[0061] In the cross-sectional view on the left it can be observed that the sidewalls of semiconductor die 22 are covered with a conformal coating 21C. As shown in the center figure, a passivation layer 21A is arranged on a bottom surface adjacent terminals T1, T3. This passivation layer comprises one or more insulation layers, such as silicon oxide or silicon nitride, on which conformal coating 21C can be arranged. Similarly, on the front surface, a passivation layer 21B is arranged adjacent terminal T2. This passivation layer comprises one or more insulation layers, such as silicon oxide or silicon nitride, and may have conformal coating 21C arranged thereon as well.

[0062] The top view in the center illustrates that terminal T2 is surrounded by passivation layer 21B. In some embodiments, terminal T2 is covered on a perimeter area thereof by passivation layer 21B, exposing only a center area of terminal T2. In other embodiments, terminal T2 covers the entire top surface of semiconductor body 22. In such embodiments, passivation layer 21B is absent.

[0063] The bottom view on the right illustrates that terminals T1, T3 are surrounded by passivation layer 21A. In some embodiments, terminals T1, T3 are covered on a perimeter area thereof by passivation layer 21A, exposing only a center area of terminals T1, T3.

[0064] FIG. 5B illustrates a further embodiment of a chip-scale package 20B in accordance with an aspect of the present disclosure. Package 20B differs from package 20A in that terminal T2 is covered by small islands of conformal coating 21C. These islands may be the result of using the method of manufacturing a chip-scale package as will be described in connection with FIG. 7.

[0065] Although FIGS. 5A, 5B illustrate three-terminal devices, the present disclosure is not limited thereto. Devices having two or more than three terminals equally fall within the scope of this disclosure.

[0066] FIG. 6 illustrates a first method for manufacturing a chip-scale package in accordance with an aspect of the present disclosure. As a first step, shown as S1_1, a wafer 30 is provided in which a plurality of two-terminal vertical devices is integrated. Each two-terminal device comprises a first terminal T1 arranged at a first surface of wafer 30 and a second terminal T2 arranged at a second surface of wafer 30. Each terminal T1, T2 is configured to cover the entire backside and frontside of the semiconductor die, respectively. Wafer 30 is arranged on a dicing foil 31 in such a manner that dicing foil 31 completely covers terminal T1. For example, terminal T1 can be pressed into dicing foil 31, as shown, or terminal T1 can fully lie against dicing foil 31.

[0067] As a next step, shown as S1_2, a sacrificial layer 32 is deposited at the second surface of wafer 30 thereby covering terminals T2. Sacrificial layer 32 may for example comprise photoresist, inks, pastes other materials with good heat absorption and a low evaporation point.

[0068] As a next step, shown as S1_3, wafer 30 is diced along dicing lines L. As a result of the dicing process, openings 33 are created in between the different semiconductor dies 30′ that correspond to different packages.

[0069] In a next step shown as S1_4, a conformal coating 34 is applied using atomic layer deposition through openings 33. Here, an alternating stack of Al.sub.2O.sub.3 and TiO.sub.2 layers is formed. In a next step shown as step S1_5, after depositing the alternating layer stack, sacrificial layer 32 is removed by means of photo-ablation. To this end, semiconductor dies 30′ may be illuminated using light having a suitable wavelength such that sacrificial layer 32 absorbs the energy and heats up quickly. Finally, sacrificial layer 32 or a part thereof ablates from semiconductor dies 30′ taking a part of conformal coating 34 with it. More in particular, the part of conformal coating 34 that is directly connected to sacrificial layer 32 will be removed together with at least a part of sacrificial layer 32 during the photo-ablation. For example, only a few nanometer of the sacrificial layer will be removed, e.g. ablated or evaporated, taking conformal coating 34 with it. After this step, the remaining part of sacrificial layer 32, if any, could be removed using a cleaning step for example using a plasma cleaning process.

[0070] As shown, after photo-ablation, sidewalls of semiconductor dies 30′ are covered by conformal coating 34 while terminals T1, T2 are free of such coating.

[0071] In FIG. 6, as well as FIGS. 7-9, terminal T2 is shown as entirely covering the second surface of wafer 30. However, the present disclosure is not limited thereto. For example, as shown in the hashed circles, embodiments are equally possible in which terminal T2 does not entirely cover the second surface of wafer 30. For example, the semiconductor die of the package may comprise an inner part and a perimeter part as shown in FIG. 1. In this case, sacrificial layer 32 may be patterned, for example using lithography techniques for creating openings that allow the ALD coating 34 to cover at least the perimeter parts of the semiconductor dies. These lithography steps can be performed prior to dicing the wafer. After performing ALD, conformal coating 34 may also cover part of terminal T2. As shown in the bottom circle, after having removed sacrificial layer 32, conformal coating 34 will cover a circumferential area of terminal T2. Furthermore, the semiconductor die may be provided with a passivation layer that can also be partially covered by conformal coating 34. This will be explained in more detail in FIG. 10.

[0072] FIG. 7 illustrates a second method for manufacturing a chip-scale package in accordance with an aspect of the present disclosure. As a first step, shown as S2_1, a wafer 40 arranged on dicing foil 41 is provided in which a plurality of two-terminal devices is integrated. This step is similar to step S1_1 shown in FIG. 6.

[0073] As a next step, shown as S2_2, wafer 40 is diced along dicing lanes L that are arranged on wafer 40. Furthermore, after dicing, a foil 42 is arranged on the second surface thereby covering terminals T2. Foil 42 comprises openings 43 that are not only arranged above the openings created during the dicing process but also above terminals T2.

[0074] As a next step, shown as S2_3, a conformal coating 44 is applied using atomic layer deposition through openings 43. Here, an alternating stack of Al.sub.2O.sub.3 and TiO.sub.2 layers is formed. In a next step, shown as S2_4, after depositing the alternating layer stack, foil 42 is removed from wafer 40. By removing foil 42, coating 44 that is arranged on and in foil 42 is also removed. Compared to FIG. 6, step S1_5, it can be observed that islands 44′ of conformal coating 44 may remain attached to terminal T2. It is further noted that the figures are not true to scale. For example, islands 44′ of conformal coating 44 may have a diameter that is substantially larger than a height of conformal coating 44.

[0075] In addition to openings above the spaces between adjacent semiconductor dies that have been created as a result of the dicing process, foil 42 may also comprise openings that are aligned with the perimeter parts of the semiconductor die as illustrated in FIG. 1. This is shown as step S2_2*. In this figure, the openings that are arranged the spaces between adjacent dies are merged with the openings above the perimeter parts of the semiconductor dies. These merged openings are referred to as openings 43*. As a result of these openings, conformal coating will also cover the perimeter parts. This can be combined with terminals T2 being exposed through one or more openings in a passivation layer on the semiconductor dies. In such case, the conformal coating may cover the semiconductor body in the perimeter part of the semiconductor die either directly or via the passivation layer, and it may cover the passivation layer that extends over terminals T2.

[0076] FIG. 8 illustrates a third method for manufacturing a chip-scale package in accordance with an aspect of the present disclosure. As a first step, shown as S3_1, a wafer 50 arranged on a dicing foil 51 is provided in which a plurality of two-terminal devices is integrated. This step differs from steps S1_1, S2_1 in that terminal T2 is formed using a metal layer stack comprising an upper part T2A and a lower part T2B. Here, upper part T2A or a part thereof forms a sacrificial layer. Lower part T2B may comprise for example TiNiVAg, TiNiAg, AuNiAg, AuAsNiAg, or combinations thereof, and upper part T2A may comprise for example Ag. In general, other metals also displaying low evaporation temperatures in combination with a high absorption of light energy for the wavelength of the light source used for the photo-ablation can be employed.

[0077] As a next step, shown as S3_2, wafer 50 is diced along dicing lanes L that are arranged on wafer 50. In between upper parts T2A openings 53 can be identified. In some embodiments, terminal T2 is formed to cover the entire second surface of wafer 50 prior to dicing. In such case, the dicing process will create openings 53 instead of the openings in the sacrificial layer already being present prior to dicing wafer 50.

[0078] As a next step, shown as S3_3, a conformal coating 54 is applied using atomic layer deposition through openings 53. Here, an alternating stack of Al.sub.2O.sub.3 and TiO.sub.2 layers is formed. in a next step shown as S3_4, after depositing the alternating layer stack, upper part T2A or a part thereof is removed by means of photo-ablation. To this end, semiconductor dies 50′ may be illuminated using light having a suitable wavelength such that upper part T2A absorbs the energy and heats up quickly. Finally, upper part T2A ablates from semiconductor dies 50′ either partly or fully taking a part of conformal coating 54 with it. More in particular, the part of conformal coating 54 that is directly connected to upper part T2A will be removed together with at least a part of upper part T2A during the photo-ablation.

[0079] To enable the perimeter part of the semiconductor die and/or terminal T2 to be at least partially covered by conformal coating 54, it may be advantageous to use a terminal T2 that does not cover the entire surface of the semiconductor die. Rather, terminal T2 may be exposed through an opening in a passivation layer, similar to what is shown in FIG. 1.

[0080] Step S3_1* illustrates an example where the perimeter part of the die and part of terminal T2 are covered by conformal coating 54. This figure does not illustrate a passivation layer that may be used.

[0081] FIG. 9 illustrates a fourth method for manufacturing a chip-scale package in accordance with an aspect of the present disclosure. As a first step, shown as S4_1, a wafer 60 arranged on a dicing foil 61 is provided in which a plurality of two-terminal devices is integrated. This step is identical to step S3_1.

[0082] As a next step, shown as S4_2, wafer 60 is partially-cut diced, such as half-cut diced, along dicing lanes L that are arranged on wafer 60. Compared to step S3_2, the semiconductor dies remain attached to each other after dicing via a remaining part of wafer 60. In between upper parts T2A openings 63 can be identified. In some embodiments, terminal T2 is formed to cover the entire second surface of wafer 60 prior to dicing. In such case, the dicing process will create openings 63 instead of the openings in the sacrificial layer already being present prior to dicing wafer 60.

[0083] As a next step, shown as S4_3, a conformal coating 64 is applied using atomic layer deposition through openings 63. This step is identical to step S3_3. In a next step shown as S4_4, after depositing conformal coating 64, upper part T2A or a part thereof is removed by means of photo-ablation. To this end, semiconductor dies 60′ may be illuminated using light having a suitable wavelength such that upper part T2A absorbs the energy and heats up quickly. Finally, upper part T2A ablates from semiconductor dies 60′ either partly or fully taking a part of conformal coating 64 with it. More in particular, the part of conformal coating 64 that is directly connected to upper part T2A will be removed together with at least a part of upper part T6A during the photo-ablation.

[0084] As a final step, shown as S4_5, semiconductor dies 60′ are fully separated, for example using a dry etch. In this method, there is less chance of contamination of the sidewalls during steps S4_3 and S4_4 as wafer 60 itself provides shielding for contaminants coming for instance from dicing foil 61. More in particular, this method can be used to prevent the glue layer of dicing foil 61 from contaminating the sidewalls of semiconductor dies 60′ before atomic layer deposition.

[0085] To enable conformal coating 64 to cover the perimeter part of semiconductor dies 60′ and an optional passivation layer, it is possible to use a different terminal T2 as shown for step S4_2*.

[0086] In FIGS. 6-9, a two-terminal device was discussed. However, the same method of manufacturing can be used for devices comprising more than two terminals. In addition, dicing foil 31, 41, 51,61 may also be provided with openings to allow conformal coating 34, 44, 54, 64 to be formed on the sidewalls of semiconductor dies 30′, 40′, 50′, 60′.

[0087] In FIGS. 6, 8 and 9, sacrificial layers 32, T2A are removed using photo-ablation. This light may be provided using a laser that scans over the surface of the diced wafer. Alternatively, a less focused light source may equally be used, for example a light source that illuminates the entire diced wafer at the same time or part of the sample using a shadow mask or other form of light patterning approach. Regardless the method of illumination, it is preferable that the sacrificial layer shows a much higher absorption of the optical energy than other components in the device. Accordingly, the material used as sacrificial layer for photo-ablation must be carefully chosen in connection with the light source that is going to be used. But differently, the sacrificial layer should have a relatively high specificity with respect to the absorption of energy from the external energy source when compared to other layers or components of the device. In this respect, it should be noted that according to another aspect of the present disclosure an energy source other than a light source can be used to cause the ablation of the sacrificial layer.

[0088] Furthermore, in FIGS. 6-9, the entire first surface of wafer 30, 40, 50, 60 is covered by dicing foil 31, 41, 51, 61. Alternatively, a small space may exist between wafer 30, 40, 50, 60 and dicing foil 31, 41, 51, 61 in regions away from terminals T1. In such case, conformal coating may also be arranged on the first surface and adjacent to terminals T1.

[0089] As shown above, the sacrificial layer can be patterned or otherwise provided in a form in which first openings are provided that are aligned with spaces between adjacent semiconductor dies, and second openings that are at least partially aligned with the perimeter parts of the second surfaces of the semiconductor dies. Possible configurations of these openings are shown in FIG. 10.

[0090] FIG. 10 (top) illustrates a cross-section of an embodiment of a chip-scale package 310 in accordance with the present disclosure in which different configurations of the conformal coating have been used.

[0091] The left part of package 310 presents a first configuration of the openings in passivation layer 320 and the openings in conformal coating 330. A top view of a semiconductor die that fully uses this configuration is shown on the bottom left. In this first configuration, the opening in conformal coating 330 is larger than the opening in passivation layer 320 for exposing terminal T2, and terminal T2 is itself larger than the opening formed in conformal coating 330 and the opening in passivation layer 320.

[0092] The right part of package 310 presents a second configuration of the openings in passivation layer and the openings in the conformal coating. A top view of a semiconductor die that fully uses this configuration is shown on the bottom right. In this second configuration, the opening in conformal coating 330 is larger than the opening in passivation layer 320 for exposing terminal T2, and terminal T2 is itself smaller than the opening formed in conformal coating 330 but larger than the opening in passivation layer 320.

[0093] It should be noted that many more configurations are possible in which conformal coating 330 covers the perimeter part of the semiconductor die either directly or via passivation layer to prevent any direct contact between the semiconductor die and electrically conductive attachment material when mounting the chip-scale package that is formed by this semiconductor die.

[0094] In the above, the present disclosure has been described using detailed embodiments thereof. However, the present disclosure is not limited to these embodiments. Instead, various modifications are possible without departing from the scope of the present disclosure which is defined by the appended claims and their equivalents.

[0095] Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

[0096] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalization thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0097] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0098] The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.