H01L23/345

Electrically or temperature activated shape-memory materials for warpage control
10861797 · 2020-12-08 · ·

A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

Method of manufacturing PCM RF switch

In fabricating a radio frequency (RF) switch, a heat spreader is provided and a heating element is deposited. A thermally conductive and electrically insulating material is deposited over the heating element. The heating element and the thermally conductive and electrically insulating material are patterned, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A layer of an upper dielectric is deposited. A conformability support layer is optionally deposited over the upper dielectric and the thermally conductive and electrically insulating material. A phase-change material is deposited over the optional conformability support layer and the underlying upper dielectric and the thermally conductive and electrically insulating material.

Multi-Phase Thermal Control Apparatus, Evaporators and Methods of Manufacture Thereof

Multi-phase thermal control systems, evaporators, variable porous wick elements, heat transfer structures, and methods for their production are provided. Two-phase evaporators for use in such multi-phase thermal control systems are also provided. Two-phase evaporators incorporate a vapor plate body having there three major layers: a vapor channel network, a wick, and a liquid channel. The vapor channel network comprises a plurality of extrusions (e.g., vapor pillars) and associated channels (e.g., vapor channels) configured to allow a vapor to flow therethrough. The wick comprises a porous body configured to be disposed between the vapor channel network of and the liquid flow reservoir.

3D FLASH MEMORY MODULE AND HEALING AND OPERATING METHODS OF 3D FLASH MEMORY
20200381050 · 2020-12-03 · ·

A three-dimensional (3D) flash memory module, a healing method of 3D flash memory, and an operating method of 3D flash memory are provided. The 3D flash memory module includes a 3D flash memory structure and a conductive layer. The 3D flash memory structure is disposed on a substrate. The conductive layer is disposed on the substrate and is adjacent to at least one side wall of the 3D flash memory structure. The conductive layer extends along the at least one side wall of the 3D flash memory structure, and each of two opposite end portions of the conductive layer has an electrical connection point in an extending direction of the conductive layer.

HEATED PINS TO COUPLE WITH SOLDER ELEMENTS
20200381388 · 2020-12-03 ·

Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the substrate, inserting the heated plurality of pins into BGA attached to a second substrate where the BGA includes a plurality of solder elements aligned with the plurality of pins and where the heated plurality of pins melt the plurality of solder elements upon insertion. The inserted plurality of pins physically and/or electrically couple the first substrate and the second substrate.

Oven controlled crystal oscillator

An oven controlled crystal oscillator consisting includes a substrate, which includes a substrate, at least one base, a crystal blank, a first cover lid, an IC chip, a heat-insulating adhesive, a heater, and a second cover lid. The top of the base is provided with a cavity, and the top of the base is connected to the substrate through conductive wires without using solder. The crystal blank is mounted in the cavity. The first cover lid seals the cavity. The IC chip is mounted on the bottom of the base. The base is mounted on the substrate through the IC chip and the heat-insulating adhesive, and the IC chip is mounted to the bottom of the base. Alternatively, the IC chip and the base are horizontally arranged. The second cover lid is mounted on the top of the substrate.

Semiconductor device

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

CRYOGENIC ON-CHIP MICROWAVE FILTER FOR QUANTUM DEVICES

An on-chip microwave filter circuit includes a substrate formed of a first material that exhibits at least a threshold level of thermal conductivity, wherein the threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The filter circuit further includes a dispersive component configured to filter a plurality of frequencies in an input signal, the dispersive component including a first transmission line disposed on the substrate, the first transmission line being formed of a second material that exhibits at least a second threshold level of thermal conductivity, where the second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The dispersive component further includes a second transmission line disposed on the substrate, the second transmission line being formed of the second material.

METHODS AND SYSTEMS FOR DISSIPATING THERMAL LOADS IN WEARABLE DEVICES

Systems and methods for manipulating the temperature of a surface are described. Described embodiments include thermal adjustment devices that may include a heatsink and that are operated in two or more modes of operation to apply a desired temperature to a user. In one operating mode the thermal adjustment device may apply a first temperature to an underlying surface while generating heat at a rate faster than the heatsink's heat dissipation rate. The thermal adjustment device may then apply a second temperature to reduce the rate of heat generation to be less than the heatsink's heat dissipation rate. These modes of operation may be applied cyclically to permit continuous operation of the thermal adjustment device. In some embodiments, the temperature profile applied when changing between the modes of operation may be selected such that the user experiences either a reduced, or substantially, neutral thermal sensation.

Method of fabricating a biological field-effect transistor (BioFET) with increased sensing area

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.