The present disclosure generally relates to a computer circuit board having an integrated voltage regulator assembly that may include a heat sink and at least one voltage regulator module board. The heat sink may have a metal plate with at least one recess in which the voltage regulator module board may be attached. The voltage regulator module board is electrically coupled to a semiconductor package and the heat sink is thermally coupled to the semiconductor package. The computer circuit board is used in high-performance computing devices including computer workstations and computer servers.

The invention relates to a composition for forming an adhesive layer, an adhesive layer, a manufacturing method for the adhesive layer, a composite material, a sheet, a heat dissipation member, an electronic device, a battery, a capacitor, an automobile component and a machine mechanism component, and the composition for forming the adhesive layer contains a polyvinyl acetal resin and a compound having an oxazoline group.

The present invention provides a high thermal conductive silicon nitride sintered body having a thermal conductivity of 50 W/m.Math.K or more and a three-point bending strength of 600 MPa or more, wherein when an arbitrary cross section of the silicon nitride sintered body is subjected to XRD analysis and highest peak intensities detected at diffraction angles of 29.3±0.2°, 29.7±0.2°, 27.0±0.2°, and 36.1±0.2° are expressed as I.sub.29.3°, I.sub.29.7°, I.sub.27.0°, and I.sub.36.1°, a peak ratio (I.sub.29.3°)/(I.sub.27.0°+I.sub.36.1°) satisfies a range of 0.01 to 0.08, and a peak ratio (I.sub.29.7°)/(I.sub.27.0°+I.sub.36.1°) satisfies a range of 0.02 to 0.16. Due to above configuration, there can be provided a silicon nitride sintered body having a high thermal conductivity of 50 W/m.Math.K or more, and excellence in insulating properties and strength.

A circuit board includes a metal circuit plate, a metallic heat diffusing plate disposed below the metal circuit plate and having an upper surface and a lower surface, a metallic heat dissipating plate below the heat diffusing plate, an insulating substrate disposed between the metal circuit plate and the heat diffusing plate, and an insulating substrate disposed between the heat diffusing plate and the heat dissipating plate. A grain diameter of metal grains contained in the heat diffusing plate decreases from each of the upper surface and the lower surface of the heat diffusing plate toward a center portion of the heat diffusing plate in a thickness direction.

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.