Implementations of a semiconductor package may include one or more semiconductor die embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead connector and a fixture portion coupled to the substrate; and a coating directly coupled to all surfaces of the substrate exposed to a coolant during operation. The fixture portion may be configured to be fastened to a fixture in an immersion cooling enclosure that may include the coolant.

Implementations of a semiconductor package may include one or more semiconductor die embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead connector and a fixture portion coupled to the substrate; and a coating directly coupled to all surfaces of the substrate exposed to a coolant during operation. The fixture portion may be configured to be fastened to a fixture in an immersion cooling enclosure that may include the coolant.

Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

A thermally conductive and electrically insulating substrate is provided. The thermally conductive and electrically insulating substrate includes a thermally conductive base, an electrically insulating layer, and one or more metal sheets. The electrically insulating layer is disposed on the thermally conductive base, and the one or more metal sheets are disposed on the electrically insulating layer. The metal sheet is allowed to have one or more chips arranged thereon, and a surface of the metal sheet where the metal sheet is allowed to be engaged with the chip is not parallel to a surface of the electrically insulating layer where the electrically insulating layer is mated with the metal sheet.

There is disclosed a system and method for transferring waste heat from integrated circuits. In an embodiment, the system comprises: a self-contained enclosure having integrated circuits therein, the self-contained enclosure further including: a first fluid circuit configured for removing waste heat from the integrated circuits; an inlet for connection from an external water tank and an outlet for connection to the external water tank, that when connected with the external water tank forms a second fluid circuit; a heat exchanger operatively connected to the first fluid circuit and the second fluid circuit, and configured to transfer thermal energy therebetween; and a control for regulating a temperature gradient and a flow rate in each of the first and second fluid circuits, such that both a desired integrated circuit operating temperature and a desired water tank temperature is achieved. A plurality of self-contained enclosures co-located with water tanks may form nodes of a distributed computing and heating network.

Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.

Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

A two-phase liquid immersion cooling system is described in which heat generating computer components cause a dielectric fluid in its liquid phase to vaporize. Advantageously an absorption/desorption unit is employed having a carbon element and a controller configured to regulate the absorption unit.

The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.