An integrated device package is disclosed. The integrated device package can include a carrier, and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity that is configured to receive a coolant. The integrated device package can include an inorganic material layer disposed at least on a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap can be directly bonded to the carrier without an intervening adhesive. The integrated device package can include an integrated device die that is disposed in the cavity and bonded to the carrier. The integrated device die can be directly bonded to the carrier without an intervening adhesive.

An integrated device package is disclosed. The integrated device package can include a carrier, and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity that is configured to receive a coolant. The integrated device package can include an inorganic material layer disposed at least on a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap can be directly bonded to the carrier without an intervening adhesive. The integrated device package can include an integrated device die that is disposed in the cavity and bonded to the carrier. The integrated device die can be directly bonded to the carrier without an intervening adhesive.

A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processor, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processor is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processor. The buffer device is disposed on the data processor. The thermally conductive shield covers the data processor, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processor.

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.

Embodiments disclosed herein include a temperature control system. In an embodiment, the temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a plurality of fluid lines between the pump and the spray chamber, where individual ones of the plurality of fluid lines are configured to provide the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber.

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., −25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.