A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

A solid-state imaging element (100) includes a first photoelectric conversion unit and a second photoelectric conversion unit (600). The first and second photoelectric conversion units (500, 600) are joined at joint surfaces facing each other, and include an upper electrode (502, 602), a lower electrode (508A, 608), a photoelectric conversion film (504, 604), and a storage electrode (510, 610). The lower electrode (508A) of the first photoelectric conversion unit (500) is connected to a charge storage unit (314) via a first through electrode (460A, 460B) penetrating a semiconductor substrate (300). The lower electrode (608) of the second photoelectric conversion unit (600) is connected to the charge storage unit (314) via: a second electrode (673) provided on a joint surface of the second photoelectric conversion unit (600); a first electrode (573) provided on a joint surface of the first photoelectric conversion unit (500); a second through electrode (560) penetrating the first photoelectric conversion unit (500); and the first through electrode (460A, 460B).

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

A semiconductor device is provided. The device comprises first semiconductor wafer comprising first BEOL structure disposed on first side of first substrate, the first BEOL structure comprising first metallization layer disposed over the first substrate, second metallization layer disposed over the first metallization layer, first storage device disposed between the first and second metallization layers, and first transistor contacting the first storage device, and a first bonding layer disposed over the first BEOL structure. The device also comprises second semiconductor wafer comprising second BEOL structure disposed on first side of second substrate, the second BEOL structure comprising third metallization layer disposed over the second substrate, fourth metallization layer disposed over the third metallization layer, second storage device disposed between the third and fourth metallization layers, and second transistor contacting the second storage device, and second bonding layer disposed over the second BEOL structure and contacting the first bonding layer.

A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.