To generate a value unique to a device in a more preferable mode. A solid-state image sensor includes a plurality of unit pixels disposed in a two-dimensional array, and a drive control unit that controls a first drive to output signals from the unit pixels included in a first unit pixel group of the plurality of unit pixels as an image signal, and a second drive to detect variations in respective signals from two or more of the unit pixels included in a second unit pixel group of the plurality of unit pixels, in which the first unit pixel group and the second unit pixel group have different structures from each other.

An apparatus for generating a binary numerical sequence is provided. The apparatus is configured to apply a first write voltage or a second write voltage, different from the first write voltage, as a write voltage to each of two or more switchable elements, and/or to apply a first read voltage or a second read voltage, different from the first read voltage, as a read voltage to each of the two or more switchable elements. Each switchable element of the two or more switchable elements is configured to output, in dependence on the write voltage applied to the switchable element and/or in dependence on the read voltage applied to the switchable element, an output voltage with a first random or pseudo-random voltage value from a first voltage value range or with a second random or pseudo-random voltage value from a second voltage value range.

A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.

Devices and methods for physical chip security are disclosed. In at least one embodiment, a security module is secured to a board to restrict physical access to an integrated circuit mounted on the security module and provides one or more contacts enabling data access to the integrated circuit.

A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10.sup.−8 Ω.Math.m and has a thickness of greater than or equal to 1 μm. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

A semiconductor structure serves to generate a physical unclonable function (PUF) code. The semiconductor structure includes a metal layer, N Titanium (Ti) structures, and N Titanium Nitride (Ti-N) structures, where N is a positive integer. The metal layer forms N metal structures. The Ti structures are respectively formed on one end of each metal structure. The Ti-N structures are respectively formed on top of the Ti structures. The metal structures and the corresponding Ti structures and the corresponding Ti-N structures respectively form a plurality of pillars. The pillars respectively provide a plurality of resistance values, and the resistance values serve to generate the PUF code.

A semiconductor package includes: a package board including a plurality of connection pads; a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip contacts a first surface of the package board, and wherein the plurality of bonding pads are respectively connected to the plurality of connection pads; and a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.