A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

An integrated circuit device is disclosed, the device comprising a protective layer and a protected circuit on a substrate, the protective layer being configured to protect the protected circuit by absorbing laser radiation targeted at the protected circuit through the substrate. The device may be configured such that removal of the protective layer causes physical damage that disables the protected circuit. The device may comprise intermediate circuitry protruding into the substrate between the protective layer and the protected circuit, wherein the physical damage that disables the protected circuit is physical damage to the intermediate circuitry. The device may comprise detection circuitry configured to detect a change in an electrical property of the device indicative of removal of the protective layer, and, in response to detecting the change in the electrical property, cause the protected circuit to be disabled.

A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.

A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

A method is provided for determining a unique identifier of a device, the device including a quantum tunnelling barrier unique to the device. The method comprises applying a potential difference across the quantum tunnelling barrier, the potential difference sufficient to enable tunnelling of charge carriers through the quantum tunnelling barrier. The method further comprises measuring an electrical signal, the electrical signal representative of a tunnelling current through the quantum tunnelling barrier, the tunnelling current characteristic of the quantum tunnelling barrier. The method further comprises determining, from the measured electrical signal, a unique identifier for the device. Related apparatuses, systems, computer-readable media and methods are also provided herein.

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

A chip tampering detector is disclosed. The chip tampering detector includes a plurality of resistor-capacitor circuits. Each resistor-capacitor circuit includes a capacitor having a planar area that covers a sensitive area of an integrated circuit of the chip. The resistor-capacitor circuits can be probed with an input signal to generate output signals. The output signals can be measured to determine respective time-constants resistor-capacitor circuits. Tampering with a chip can alter the capacitance of a capacitor covering a sensitive area. Accordingly, a significant change of a time-constant of one or more of the resistor-capacitor circuits can be used to detect chip tampering.

According to various embodiments, an integrated circuit is described comprising a plurality of subcircuits having different signal transfer reaction times, a control circuit configured to form two competing paths from the plurality of subcircuits in response to a control signal, an input circuit configured to supply an input signal to the two competing paths and an output circuit configured to generate an output value depending on which of the competing paths has transferred the input signal with shorter reaction time.

Embodiments of the present disclosure provide a detection circuit for a laser fault injection attack on a chip and a security chip. The detection circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a photosensitive element, a first NMOS transistor, and a second NMOS transistor. A drain of the first NMOS transistor is configured to output a first voltage signal, and a drain of the second NMOS transistor is configured to output a second voltage signal. The first voltage signal and the second voltage signal are configured to indicate that the chip is attacked by laser fault injection, thereby realizing detection of the laser fault injection attack, and ensuring the robustness and security of the chips.

The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.