A semiconductor device includes wiring that is formed by a conductive body extending, via an insulating film, on a front surface of a semiconductor substrate, and an insulating layer that covers the front surface of the semiconductor substrate including the wiring. Gaps are provided extending from an upper surface of the wiring to a lower portion of the insulating film.

A microwave system includes a molding compound layer having opposing first and second surfaces, an integrated circuit device at least partially surrounded by said molding compound layer to define a fan-out area located laterally outside the integrated circuit device's outline, a plurality of through-mold vias within said fan-out area extending through said molding compound layer between said first and second surfaces, a re-distribution layer stack extending parallel to said second surface and comprising conducting signal paths, and a substrate comprising a first surface extending parallel to the molding compound layer. The re-distribution layer stack is positioned on top of an array of solder balls carried by the substrate. The system also includes two coupling slots arranged on different levels to resonantly couple with each other, and at least one hollow waveguide with an open (coupling) aperture at one end in direct proximity of one of said two coupling slots.

In one embodiment, a semiconductor device includes a first insulator, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided on the first pad in the second insulator. Furthermore, the first insulator includes a first film that is in contact with the first pad and the second insulator, and a second film provided at an interval from the first pad and the second insulator, and including a portion provided at a same height as at least a portion of the first pad.

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

An IC device includes an interlayer dielectric (ILD), a first tower structure embedded in the ILD, and a first ring region including a portion of the ILD that extends around the first tower structure. The first tower structure includes a plurality of first conductive patterns in a plurality of metal layers, and a plurality of first vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of first conductive patterns and the plurality of first vias are coupled to each other to form the first tower structure. The plurality of first conductive patterns is confined by the first ring region, without extending beyond the first ring region. The first tower structure is a dummy tower structure.

A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory array, logic-side dielectric material layers, and logic-side metal interconnect structures and first logic-side bonding pads that are bonded to a respective one of the first memory-side bonding pads. The backside peripheral circuit includes a second subset of the logic devices located on a second side of the doped semiconductor material layer.