Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

A method for manufacturing a semiconductor device includes providing a semiconductor element having an electrode terminal, forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminal and a second surface opposite to the first surface, providing an imprint mold having a third surface and a protrusion protruding from the third surface, forming an opening in the resist by disposing the imprint mold on the second surface of the resist and inserting the protrusion into the resist, the third surface of the imprint mold facing the second surface of the resist, the protrusion being aligned with the electrode terminal, curing the resist by applying energy to the resist, widening the opening in a radial direction of the opening by causing the resist to react with a developer, and forming a bump by filling the opening with metal, in which the forming of the opening in the resist is performed in a state where a gap is provided between the second surface of the resist and the third surface of the imprint mold.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

A device that includes a first board, a second board, and coaxial cable coupled to the first board and the second board. The coaxial cable includes a multi-line coaxial cable configured to provide at least two electrical paths for electrical currents between the first board and the second board. A first plug is coupled to the first board. A second plug is coupled to the second board. The coaxial cable includes a first receptable and a second receptable. The first receptable is configured to couple to the first plug. The second receptable is configured to couple to the second plug. The coaxial cable is configured to provide (i) a first electrical path for a first electrical current between the first board and the second board, and (ii) a second electrical path for a second electrical current between the first board and the second board.

Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

A method for manufacturing an electronic device includes providing a substrate, forming a plurality of connecting pads and a plurality of conductive portions partially overlapped by the plurality of connecting pads on a surface of the substrate; forming a plurality of conductive lines on the substrate, wherein the plurality of conductive lines are electrically connected to the plurality of conductive portions; and bonding a plurality of light emitting units to the plurality of connecting pads. The method may further includes identifying a defective light emitting unit from the plurality of light emitting units; removing the defective light emitting unit from a corresponding position on the substrate; and bonding-another light emitting unit to the corresponding position.

A method for underfilling an electronic circuit assembly may include mounting one or more structures to a substrate, mounting one or more spacers to the substrate at one or more positions, respectively, to form one or more passages between the one or more spacers and the one or more structures, dispensing underfill to the one or more passages, and curing the underfill to secure the one or more structures to the substrate. The one or more structures may include one or more dies.

A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

A printed structure includes a substrate comprising a substrate surface, a substrate circuit disposed in or on in a circuit area of the substrate surface, a substrate post protruding from the substrate surface exterior to the circuit area, and a component having a component top side and a component bottom side opposite the component top side. The component bottom side can be disposed on the substrate post and adhered to the substrate surface forming an air gap between the component bottom side and the substrate circuit. The substrate post can comprise a substrate post material that is a cured adhesive. Some embodiments comprise a substrate electrode and the component comprises an electrically conductive connection post extending from the component bottom side toward the substrate in electrical contact with the substrate electrode.