Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

A method for manufacturing a thin sheet-like bonding member, including applying a paste including first particles including a first metal, second particles including a second metal having a lower melting point than the first metal, and a solvent to a surface of a base material made of a substance that does not react with the second metal; heating the paste at a temperature lower than a melting point of the first metal and higher than the melting point of the second metal to form a thin sheet-like bonding member on the surface of the base material; and peeling the thin sheet-like bonding member from the base material to obtain the thin sheet-like bonding member.

A display module is disclosed. The display module includes a pixel that includes: first to third self-luminescence elements that are configured to emit light of an ultraviolet wavelength range; first to third color conversion layers respectively corresponding to light emitting surfaces of the first to third self-luminescence elements; a first color filter and a second color filter respectively corresponding to the first color conversion layer and the second color conversion layer; a transparent resin layer corresponding to the third color conversion layer and disposed on a same plane as a plane at which the first color filter and the second color filter are positioned; a transparent cover layer that covers the first color filter, the second color filter, and the transparent resin layer; and an ultraviolet (UV) cutoff filter that covers the transparent cover layer.

A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

Provided is a flux that allows soldering to be performed without requiring a step of removing a Cu-OSP film even with a Cu-OSP processed substrate. This flux containing rosin, an organic acid, a benzimidazole-based compound, and a solvent is characterized in that 30% by mass or more and 70% by mass or less of the rosin, 1% by mass or more and 10% by mass or less of the organic acid, 0.2% by mass or more and 10% by mass or less of the benzimidazole-based compound, and 20% by mass or more and 60% by mass or less of the solvent, wherein the benzimidazole-based compound is composed of at least one of 2-alkylbenzimidazole and a salt of 2-alkylbenzimidazole hydrohalide.

A solder material is provided. The solder material may include a first amount of particles having particle sizes forming a first size distribution, a second amount of particles having particle sizes forming a second size distribution, the particle sizes of the second size distribution being larger than the particle sizes of the first size distribution, and a solder base material in which the first amount of particles and the second amount of particles is distributed. The first amount of particles and the second amount of particles consist of or essentially consist of a metal of a first group of metals. The first group of metals includes copper, silver, gold, palladium, platinum, iron, cobalt, and aluminum. The solder base material includes a metal of a second group of metals. The second group of metals includes tin, indium, zinc, gallium, germanium, antimony, and bismuth.

A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.

A transparent display panel, a method for manufacturing the same, and a transparent display device are provided. the transparent display panel includes a first display substrate including: a first substrate and first pixel units thereon; and a second display substrate including: a second substrate and second pixel units thereon, the second pixel units are in one-to-one correspondence with the first pixel units, each first pixel unit includes a first display unit and a first transparent unit, and each second pixel unit includes a second display unit and a second transparent unit, an orthographic projection of the first display unit on the second substrate substantially coincides with that of the corresponding second display unit on the second substrate, and an orthographic projection of the first transparent unit on the second substrate substantially coincides with that of the corresponding second transparent unit on the second substrate.

An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.